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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is n ecessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
h8s/2355 series hd6432355, hd6472355 h8s/2353 hd6432353 h8s/2393 hd6432393 hardware manual ade-602-112b rev. 3.0 3/11/03 hitachi, ltd www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
preface the h8s/2355 series is a series of high-performance microcontrollers with a 32-bit h8s/2000 cpu core, and a set of on-chip supporting functions required for system configuration. the h8s/2000 cpu can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. the cpu can handle a 16 mbyte linear address space (architecturally 4 gbytes). programs based on the high-level language c can also be run efficiently. the address space is divided into eight areas. the data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. on-chip memory consists of large-capacity rom and ram. prom (ztata*) and mask rom versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. on-chip supporting functions include a 16-bit timer pulse unit (tpu), 8-bit timers, watchdog timer (wdt), serial communication interface (sci), a/d converter, d/a converter, and i/o ports. an on-chip data transfer controller (dtc) is also provided, enabling high-speed data transfer without cpu intervention. use of the h8s/2355 series enables compact, high-performance systems to be implemented easily. this manual describes the hardware of the h8s/2355 series. refer to the h8s/2600 series and h8s/2000 series programming manual for a detailed description of the instruction set. note: * ztat is a trademark of hitachi, ltd. there is no prom version of the h8s/2393. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
main revisions and additions in this edition page section revision contents all h8s/2393 added 4 table 1-1 overview product lineup [amendments] amendments associated with h8s/2393 addition 6 figure 1-2 block diagram (h8s/2393) [addition] 9, 10 figure 1-5 h8s/2393 pin arrangement (tfp-120: top view) figure 1-6 h8s/2393 pin arrangement (tfp-128: top view) [addition] 81, 82 figure 3-3 memory map in each operating mode in the h8s/2393 [addition] 225 8.5.1 overview (port 4) [amendment] port 4 pins also function ..... as a/d converter analog input pins (an0 to an7) in the h8s/2393. 421 table 12-3 brr settings for various bit rates (asynchronous mode) bit rate: 38400 [amendment] error entries when ? = 4 mhz amended to . 502 14.2.3 a/d control register (adcr) [amendment] description of bits 7 and 6 bit 7 bit 6 trgs1 trgs0 description 0 0 a/d conversion start by external trigger is disabled (initial value) 1 a/d conversion start by external trigger (tpu) is enabled 1 0 a/d conversion start by external trigger (8-bit timer) is enabled 1 a/d conversion start by external trigger pin ( adtrg ) is enabled table 14.6 analog pin specifications [deletion] 517 section 15 d/a converter [amendment] (not supported in h8s/2393) 533 figure 17-2 wiring of 120-pin/32-pin socket adapter pin 4 of fp-128 [amendment] changed to open. 558 table 19-3 mstp bits and corresponding on-chip supporting modules bit mstp10 [addition] * in the h8s/2393 bit 10 can be read and written to but has no effect on operation, as a d/a converter is not supported. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
page section revision contents 570 table 20-2 dc characteristics (3) [additions] dc characteristics added for following conditions. conditions: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v* 1 , t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) 574 576 578 586 591 592 table 20-4 clock timing table 20-5 control signal timing table 20-6 bus timing table 20-7 timing of on-chip supporting modules table 20-8 a/d conversion characteristics table 20-9 d/a conversion characteristics [additions] additions for condition c condition c: (mask rom version only) v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ? = 2 to 13 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) 642 table a-5 number of cycles in instruction execution eepmov instruction, byte data access [amendments] 2n + 2 * 2 note: 2. when n bytes of data are transferred. 672 b.1 addresses hffa4 dadr0 * 4 hffa5 dadr1 * 4 hffa6 dacr * 4 [amendments] note: 4. in the h8s/2393 these bits are reserved, as a d/a converter is not supported. 781 to 785 figure c-1 (a) port 1 block diagram (pins p1 0 , p1 1 , p1 4 and p1 6 ) figure c-1 (b) port 1 block diagram (pins p1 2 , p1 3 , p1 5 , and p1 7 ) figure c-2 (a) port 2 block diagram (pins p2 0 and p2 1 ) figure c-2 (b) port 2 block diagram (pins p2 2 and p2 4 ) figure c-2 (c) port 2 block diagram (pins p2 3 and p2 5 ) [deletion] note: * priority order: output compare output/pwm output > dr output www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
page section revision contents 786 figure c-2 (d) port 2 block diagram (pins p2 6 and p2 7 ) [deletion] note: * priority order: output compare output/pwm output > compare match output > dr output 790 figure c-4 (a) port 4 block diagram [amendments] (pins p4 0 to p4 5 in h8s/2355 and h8s/2353, pins p4 0 to p4 7 in h8s/2393) 793 figure c-5 (c) port 5 block diagram (pin p5 2 ) [deletion] note: * priority order: serial clock input > serial clock output > dr output 821, 822 appendix e pin states at power-on [additions] 824 table g.1 h8s/2355 series product code lineup [amendments] amendments associated with addition of h8s/2393 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
i contents section 1 overview ............................................................................................................ 1 1.1 overview.................................................................................................................... ........ 1 1.2 block diagram ............................................................................................................... .... 5 1.3 pin description............................................................................................................. ...... 7 1.3.1 pin arrangement ................................................................................................... 7 1.3.2 pin functions in each operating mode................................................................ 11 1.3.3 pin functions ........................................................................................................ 16 section 2 cpu ..................................................................................................................... 23 2.1 overview.................................................................................................................... ........ 23 2.1.1 features ................................................................................................................. 2 3 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu................................... 24 2.1.3 differences from h8/300 cpu ............................................................................. 25 2.1.4 differences from h8/300h cpu .......................................................................... 25 2.2 cpu operating modes ....................................................................................................... 26 2.3 address space............................................................................................................... ..... 31 2.4 register configuration ...................................................................................................... .32 2.4.1 overview............................................................................................................... 32 2.4.2 general registers.................................................................................................. 33 2.4.3 control registers .................................................................................................. 34 2.4.4 initial register values .......................................................................................... 36 2.5 data formats................................................................................................................ ...... 37 2.5.1 general register data formats............................................................................. 37 2.5.2 memory data formats.......................................................................................... 39 2.6 instruction set ............................................................................................................. ....... 40 2.6.1 overview............................................................................................................... 40 2.6.2 instructions and addressing modes...................................................................... 41 2.6.3 table of instructions classified by function........................................................ 43 2.6.4 basic instruction formats ..................................................................................... 53 2.7 addressing modes and effective address calculation...................................................... 54 2.7.1 addressing mode.................................................................................................. 54 2.7.2 effective address calculation .............................................................................. 57 2.8 processing states........................................................................................................... ..... 61 2.8.1 overview............................................................................................................... 61 2.8.2 reset state ............................................................................................................ 62 2.8.3 exception-handling state ..................................................................................... 63 2.8.4 program execution state ...................................................................................... 66 2.8.5 bus-released state................................................................................................ 66 2.8.6 power-down state ................................................................................................ 66 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
ii 2.9 basic timing................................................................................................................ ...... 67 2.9.1 overview............................................................................................................... 67 2.9.2 on-chip memory (rom, ram).......................................................................... 67 2.9.3 on-chip supporting module access timing ....................................................... 69 2.9.4 external address space access timing ............................................................... 70 section 3 mcu operating modes ................................................................................. 71 3.1 overview.................................................................................................................... ........ 71 3.1.1 operating mode selection .................................................................................... 71 3.1.2 register configuration.......................................................................................... 72 3.2 register descriptions ....................................................................................................... .. 72 3.2.1 mode control register (mdcr) .......................................................................... 72 3.2.2 system control register (syscr)....................................................................... 73 3.3 operating mode descriptions ............................................................................................ 74 3.3.1 mode 1 .................................................................................................................. 74 3.3.2 mode 2 .................................................................................................................. 74 3.3.3 mode 3 .................................................................................................................. 74 3.3.4 mode 4 .................................................................................................................. 74 3.3.5 mode 5 .................................................................................................................. 75 3.3.6 mode 6 .................................................................................................................. 75 3.3.7 mode 7 .................................................................................................................. 75 3.4 pin functions in each operating mode ............................................................................. 76 3.5 memory map in each operating mode ............................................................................. 76 section 4 exception handling ........................................................................................ 83 4.1 overview.................................................................................................................... ........ 83 4.1.1 exception handling types and priority................................................................ 83 4.1.2 exception handling operation ............................................................................. 84 4.1.3 exception vector table ........................................................................................ 84 4.2 reset....................................................................................................................... ............ 86 4.2.1 overview............................................................................................................... 86 4.2.2 reset types........................................................................................................... 86 4.2.3 reset sequence ..................................................................................................... 87 4.2.4 interrupts after reset............................................................................................. 88 4.2.5 state of on-chip supporting modules after reset release.................................. 88 4.3 traces ...................................................................................................................... ........... 89 4.4 interrupts .................................................................................................................. .......... 90 4.5 trap instruction............................................................................................................ ...... 91 4.6 stack status after exception handling .............................................................................. 92 4.7 notes on use of the stack.................................................................................................. 9 3 section 5 interrupt controller ......................................................................................... 95 5.1 overview.................................................................................................................... ........ 95 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
iii 5.1.1 features ................................................................................................................. 9 5 5.1.2 block diagram...................................................................................................... 96 5.1.3 pin configuration.................................................................................................. 97 5.1.4 register configuration.......................................................................................... 97 5.2 register descriptions ....................................................................................................... .. 98 5.2.1 system control register (syscr)....................................................................... 98 5.2.2 interrupt priority registers a to k (ipra to iprk) ............................................ 99 5.2.3 irq enable register (ier) ................................................................................... 100 5.2.4 irq sense control registers h and l (iscrh, iscrl) ..................................... 101 5.2.5 irq status register (isr) .................................................................................... 102 5.3 interrupt sources........................................................................................................... ..... 103 5.3.1 external interrupts ................................................................................................ 103 5.3.2 internal interrupts.................................................................................................. 104 5.3.3 interrupt exception handling vector table ......................................................... 104 5.4 interrupt operation......................................................................................................... .... 108 5.4.1 interrupt control modes and interrupt operation ................................................ 108 5.4.2 interrupt control mode 0...................................................................................... 111 5.4.3 interrupt control mode 2...................................................................................... 113 5.4.4 interrupt exception handling sequence ............................................................... 115 5.4.5 interrupt response times ..................................................................................... 117 5.5 usage notes ................................................................................................................. ...... 118 5.5.1 contention between interrupt generation and disabling ..................................... 118 5.5.2 instructions that disable interrupts....................................................................... 119 5.5.3 times when interrupts are disabled ..................................................................... 119 5.5.4 interrupts during execution of eepmov instruction .......................................... 119 5.6 dtc activation by interrupt.............................................................................................. 120 5.6.1 overview............................................................................................................... 120 5.6.2 block diagram...................................................................................................... 120 5.6.3 operation .............................................................................................................. 121 section 6 bus controller .................................................................................................. 123 6.1 overview.................................................................................................................... ........ 123 6.1.1 features ................................................................................................................. 1 23 6.1.2 block diagram...................................................................................................... 124 6.1.3 pin configuration.................................................................................................. 125 6.1.4 register configuration.......................................................................................... 125 6.2 register descriptions ....................................................................................................... .. 126 6.2.1 bus width control register (abwcr) ............................................................... 126 6.2.2 access state control register (astcr).............................................................. 127 6.2.3 wait control registers h and l (wcrh, wcrl) .............................................. 128 6.2.4 bus control register h (bcrh) .......................................................................... 131 6.2.5 bus control register l (bcrl) ........................................................................... 133 6.3 overview of bus control ................................................................................................... 13 4 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
iv 6.3.1 area partitioning................................................................................................... 134 6.3.2 bus specifications ................................................................................................ 136 6.3.3 memory interfaces................................................................................................ 137 6.3.4 advanced mode.................................................................................................... 137 6.3.5 areas in normal mode.......................................................................................... 138 6.3.6 chip select signals ............................................................................................... 139 6.4 basic bus interface ......................................................................................................... ... 140 6.4.1 overview............................................................................................................... 140 6.4.2 data size and data alignment.............................................................................. 140 6.4.3 valid strobes........................................................................................................ 142 6.4.4 basic timing......................................................................................................... 143 6.4.5 wait control ......................................................................................................... 151 6.5 burst rom interface......................................................................................................... . 153 6.5.1 overview............................................................................................................... 153 6.5.2 basic timing......................................................................................................... 153 6.5.3 wait control.......................................................................................................... 155 6.6 idle cycle .................................................................................................................. ......... 156 6.6.1 operation .............................................................................................................. 156 6.6.2 pin states in idle cycle ......................................................................................... 159 6.7 bus release................................................................................................................. ....... 160 6.7.1 overview............................................................................................................... 160 6.7.2 operation .............................................................................................................. 160 6.7.3 pin states in external bus released state ............................................................ 161 6.7.4 transition timing ................................................................................................. 162 6.7.5 usage note............................................................................................................ 163 6.8 bus arbitration............................................................................................................. ...... 163 6.8.1 overview............................................................................................................... 163 6.8.2 operation .............................................................................................................. 163 6.8.3 bus transfer timing ............................................................................................. 164 6.8.4 external bus release usage note ........................................................................ 164 6.9 resets and the bus controller............................................................................................ 164 section 7 data transfer controller ............................................................................... 165 7.1 overview.................................................................................................................... ........ 165 7.1.1 features ................................................................................................................. 1 65 7.1.2 block diagram...................................................................................................... 166 7.1.3 register configuration.......................................................................................... 167 7.2 register descriptions ....................................................................................................... .. 168 7.2.1 dtc mode register a (mra) ............................................................................. 168 7.2.2 dtc mode register b (mrb).............................................................................. 170 7.2.3 dtc source address register (sar) .................................................................. 171 7.2.4 dtc destination address register (dar) .......................................................... 171 7.2.5 dtc transfer count register a (cra) ............................................................... 171 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
v 7.2.6 dtc transfer count register b (crb)................................................................ 172 7.2.7 dtc enable registers (dtcer).......................................................................... 172 7.2.8 dtc vector register (dtvecr) ........................................................................ 173 7.2.9 module stop control register (mstpcr)........................................................... 174 7.3 operation................................................................................................................... ......... 175 7.3.1 overview............................................................................................................... 175 7.3.2 activation sources................................................................................................ 177 7.3.3 dtc vector table ................................................................................................ 178 7.3.4 location of register information in address space............................................. 181 7.3.5 normal mode........................................................................................................ 182 7.3.6 repeat mode ......................................................................................................... 183 7.3.7 block transfer mode............................................................................................ 184 7.3.8 chain transfer ...................................................................................................... 186 7.3.9 operation timing.................................................................................................. 187 7.3.10 number of dtc execution states ........................................................................ 188 7.3.11 procedures for using dtc.................................................................................... 190 7.3.12 examples of use of the dtc................................................................................ 191 7.4 interrupts .................................................................................................................. .......... 193 7.5 usage notes ................................................................................................................. ...... 193 section 8 i/o ports ............................................................................................................. 195 8.1 overview.................................................................................................................... ........ 195 8.2 port 1...................................................................................................................... ............ 200 8.2.1 overview............................................................................................................... 200 8.2.2 register configuration.......................................................................................... 200 8.2.3 pin functions ........................................................................................................ 202 8.3 port 2...................................................................................................................... ............ 210 8.3.1 overview............................................................................................................... 210 8.3.2 register configuration.......................................................................................... 210 8.3.3 pin functions ........................................................................................................ 212 8.4 port 3...................................................................................................................... ............ 220 8.4.1 overview............................................................................................................... 220 8.4.2 register configuration.......................................................................................... 220 8.4.3 pin functions ........................................................................................................ 223 8.5 port 4...................................................................................................................... ............ 225 8.5.1 overview............................................................................................................... 225 8.5.2 register configuration.......................................................................................... 226 8.5.3 pin functions ........................................................................................................ 226 8.6 port 5...................................................................................................................... ............ 227 8.6.1 overview............................................................................................................... 227 8.6.2 register configuration.......................................................................................... 227 8.6.3 pin functions ........................................................................................................ 230 8.7 port 6...................................................................................................................... ............ 231 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
vi 8.7.1 overview............................................................................................................... 231 8.7.2 register configuration.......................................................................................... 232 8.7.3 pin functions ........................................................................................................ 234 8.8 port a ...................................................................................................................... ........... 236 8.8.1 overview............................................................................................................... 236 8.8.2 register configuration.......................................................................................... 237 8.8.3 pin functions ........................................................................................................ 240 8.8.4 mos input pull-up function................................................................................ 242 8.9 port b ...................................................................................................................... ........... 243 8.9.1 overview............................................................................................................... 243 8.9.2 register configuration.......................................................................................... 244 8.9.3 pin functions ........................................................................................................ 246 8.9.4 mos input pull-up function................................................................................ 247 8.10 port c ..................................................................................................................... ............ 248 8.10.1 overview............................................................................................................... 24 8 8.10.2 register configuration.......................................................................................... 249 8.10.3 pin functions ........................................................................................................ 251 8.10.4 mos input pull-up function................................................................................ 253 8.11 port d ..................................................................................................................... ............ 254 8.11.1 overview............................................................................................................... 25 4 8.11.2 register configuration.......................................................................................... 255 8.11.3 pin functions ........................................................................................................ 257 8.11.4 mos input pull-up function................................................................................ 258 8.12 port e..................................................................................................................... ............. 259 8.12.1 overview............................................................................................................... 25 9 8.12.2 register configuration.......................................................................................... 260 8.12.3 pin functions ........................................................................................................ 262 8.12.4 mos input pull-up function................................................................................ 263 8.13 port f..................................................................................................................... ............. 264 8.13.1 overview............................................................................................................... 26 4 8.13.2 register configuration.......................................................................................... 265 8.13.3 pin functions ........................................................................................................ 267 8.14 port g ..................................................................................................................... ............ 269 8.14.1 overview............................................................................................................... 26 9 8.14.2 register configuration.......................................................................................... 270 8.14.3 pin functions ........................................................................................................ 272 section 9 16-bit timer pulse unit (tpu) .................................................................. 275 9.1 overview.................................................................................................................... ........ 275 9.1.1 features ................................................................................................................. 2 75 9.1.2 block diagram...................................................................................................... 279 9.1.3 pin configuration.................................................................................................. 280 9.1.4 register configuration.......................................................................................... 282 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
vii 9.2 register descriptions ....................................................................................................... .. 284 9.2.1 timer control register (tcr).............................................................................. 284 9.2.2 timer mode register (tmdr)............................................................................. 289 9.2.3 timer i/o control register (tior)...................................................................... 291 9.2.4 timer interrupt enable register (tier)............................................................... 304 9.2.5 timer status register (tsr) ................................................................................ 307 9.2.6 timer counter (tcnt)......................................................................................... 310 9.2.7 timer general register (tgr) ............................................................................. 311 9.2.8 timer start register (tstr) ................................................................................ 312 9.2.9 timer synchro register (tsyr).......................................................................... 313 9.2.10 module stop control register (mstpcr)........................................................... 314 9.3 interface to bus master..................................................................................................... . 315 9.3.1 16-bit registers .................................................................................................... 315 9.3.2 8-bit registers ...................................................................................................... 315 9.4 operation................................................................................................................... ......... 317 9.4.1 overview............................................................................................................... 317 9.4.2 basic functions..................................................................................................... 318 9.4.3 synchronous operation ........................................................................................ 324 9.4.4 buffer operation ................................................................................................... 326 9.4.5 cascaded operation .............................................................................................. 330 9.4.6 pwm modes ......................................................................................................... 332 9.4.7 phase counting mode ........................................................................................... 337 9.5 interrupts .................................................................................................................. .......... 343 9.5.1 interrupt sources and priorities ............................................................................ 343 9.5.2 dtc activation .................................................................................................... 345 9.5.3 a/d converter activation..................................................................................... 345 9.6 operation timing ............................................................................................................ ... 346 9.6.1 input/output timing ............................................................................................. 346 9.6.2 interrupt signal timing ........................................................................................ 350 9.7 usage notes ................................................................................................................. ...... 354 section 10 8-bit timers ...................................................................................................... 365 10.1 overview................................................................................................................... ......... 365 10.1.1 features ................................................................................................................. 365 10.1.2 block diagram...................................................................................................... 366 10.1.3 pin configuration.................................................................................................. 367 10.1.4 register configuration.......................................................................................... 367 10.2 register descriptions ...................................................................................................... ... 368 10.2.1 timer counters 0 and 1 (tcnt0, tcnt1).......................................................... 368 10.2.2 time constant registers a0 and a1 (tcora0, tcora1)................................ 368 10.2.3 time constant registers b0 and b1 (tcorb0, tcorb1) ................................ 369 10.2.4 time control registers 0 and 1 (tcr0, tcr1) ................................................... 369 10.2.5 timer control/status registers 0 and 1 (tcsr0, tcsr1) .................................. 371 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
viii 10.2.6 module stop control register (mstpcr)........................................................... 374 10.3 operation.................................................................................................................. .......... 375 10.3.1 tcnt incrementation timing.............................................................................. 375 10.3.2 compare match timing........................................................................................ 376 10.3.3 timing of external reset on tcnt .................................................................. 378 10.3.4 timing of overflow flag (ovf) setting.............................................................. 378 10.3.5 operation with cascaded connection .................................................................. 379 10.4 interrupts ................................................................................................................. ........... 380 10.4.1 interrupt sources and dtc activation ................................................................. 380 10.4.2 a/d converter activation..................................................................................... 380 10.5 sample application......................................................................................................... ... 381 10.6 usage notes ................................................................................................................ ....... 382 10.6.1 contention between tcnt write and clear ........................................................ 382 10.6.2 contention between tcnt write and increment................................................. 383 10.6.3 contention between tcor write and compare match ....................................... 384 10.6.4 contention between compare matches a and b.................................................. 385 10.6.5 switching of internal clocks and tcnt operation ............................................ 385 10.6.6 usage note............................................................................................................ 387 section 11 watchdog timer .............................................................................................. 389 11.1 overview................................................................................................................... ......... 389 11.1.1 features ................................................................................................................. 389 11.1.2 block diagram...................................................................................................... 390 11.1.3 pin configuration.................................................................................................. 391 11.1.4 register configuration.......................................................................................... 391 11.2 register descriptions ...................................................................................................... ... 392 11.2.1 timer counter (tcnt) ........................................................................................ 392 11.2.2 timer control/status register (tcsr) ................................................................ 392 11.2.3 reset control/status register (rstcsr) ............................................................ 394 11.2.4 notes on register access...................................................................................... 396 11.3 operation.................................................................................................................. .......... 398 11.3.1 watchdog timer operation .................................................................................. 398 11.3.2 interval timer operation ...................................................................................... 399 11.3.3 timing of setting overflow flag (ovf).............................................................. 399 11.3.4 timing of setting of watchdog timer overflow flag (wovf).......................... 400 11.4 interrupts ................................................................................................................. ........... 401 11.5 usage notes ................................................................................................................ ....... 401 11.5.1 contention between timer counter (tcnt) write and increment...................... 401 11.5.2 changing value of cks2 to cks0 ...................................................................... 401 11.5.3 switching between watchdog timer mode and interval timer mode................ 402 11.5.4 system reset by wdtovf signal ...................................................................... 402 11.5.5 internal reset in watchdog timer mode.............................................................. 402 www.datasheet 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ix section 12 serial communication interface (sci) ..................................................... 403 12.1 overview................................................................................................................... ......... 403 12.1.1 features ................................................................................................................. 403 12.1.2 block diagram...................................................................................................... 405 12.1.3 pin configuration.................................................................................................. 406 12.1.4 register configuration.......................................................................................... 407 12.2 register descriptions ...................................................................................................... ... 408 12.2.1 receive shift register (rsr) ............................................................................... 408 12.2.2 receive data register (rdr)............................................................................... 408 12.2.3 transmit shift register (tsr).............................................................................. 409 12.2.4 transmit data register (tdr).............................................................................. 409 12.2.5 serial mode register (smr) ................................................................................ 410 12.2.6 serial control register (scr) .............................................................................. 413 12.2.7 serial status register (ssr) ................................................................................. 417 12.2.8 bit rate register (brr) ....................................................................................... 420 12.2.9 smart card mode register (scmr)..................................................................... 429 12.2.10 module stop control register (mstpcr)........................................................... 430 12.3 operation.................................................................................................................. .......... 431 12.3.1 overview............................................................................................................... 43 1 12.3.2 operation in asynchronous mode........................................................................ 433 12.3.3 multiprocessor communication function ............................................................ 444 12.3.4 operation in clocked synchronous mode............................................................ 452 12.4 sci interrupts ............................................................................................................. ........ 460 12.5 usage notes ................................................................................................................ ....... 462 section 13 smart card interface ...................................................................................... 467 13.1 overview................................................................................................................... ......... 467 13.1.1 features ................................................................................................................. 467 13.1.2 block diagram...................................................................................................... 468 13.1.3 pin configuration.................................................................................................. 469 13.1.4 register configuration.......................................................................................... 470 13.2 register descriptions ...................................................................................................... ... 471 13.2.1 smart card mode register (scmr)..................................................................... 471 13.2.2 serial status register (ssr) ................................................................................. 472 13.2.3 serial mode register (smr) ................................................................................ 473 13.2.4 serial control register (scr) .............................................................................. 474 13.3 operation.................................................................................................................. .......... 475 13.3.1 overview............................................................................................................... 47 5 13.3.2 pin connections .................................................................................................... 476 13.3.3 data format .......................................................................................................... 477 13.3.4 register settings ................................................................................................... 479 13.3.5 clock .................................................................................................................... . 481 13.3.6 data transfer operations...................................................................................... 483 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
x 13.3.7 operation in gsm mode ...................................................................................... 490 13.4 usage notes ................................................................................................................ ....... 491 section 14 a/d converter .................................................................................................. 495 14.1 overview................................................................................................................... ......... 495 14.1.1 features ................................................................................................................. 495 14.1.2 block diagram...................................................................................................... 496 14.1.3 pin configuration.................................................................................................. 497 14.1.4 register configuration.......................................................................................... 498 14.2 register descriptions ...................................................................................................... ... 499 14.2.1 a/d data registers a to d (addra to addrd).............................................. 499 14.2.2 a/d control/status register (adcsr) ................................................................ 500 14.2.3 a/d control register (adcr) ............................................................................. 502 14.2.4 module stop control register (mstpcr)........................................................... 503 14.3 interface to bus master.................................................................................................... .. 504 14.4 operation.................................................................................................................. .......... 505 14.4.1 single mode (scan = 0) ..................................................................................... 505 14.4.2 scan mode (scan = 1)........................................................................................ 507 14.4.3 input sampling and a/d conversion time .......................................................... 509 14.4.4 external trigger input timing.............................................................................. 510 14.5 interrupts ................................................................................................................. ........... 511 14.6 usage notes ................................................................................................................ ....... 511 section 15 d/a converter (not supported in h8s/2393) ........................................ 517 15.1 overview................................................................................................................... ......... 517 15.1.1 features ................................................................................................................. 517 15.1.2 block diagram...................................................................................................... 518 15.1.3 pin configuration.................................................................................................. 519 15.1.4 register configuration.......................................................................................... 519 15.2 register descriptions ...................................................................................................... ... 520 15.2.1 d/a data registers 0 and 1 (dadr0, dadr1).................................................. 520 15.2.2 d/a control register (dacr) ............................................................................. 520 15.2.3 module stop control register (mstpcr)........................................................... 522 15.3 operation.................................................................................................................. .......... 523 section 16 ram .................................................................................................................... 525 16.1 overview................................................................................................................... ......... 525 16.1.1 block diagram...................................................................................................... 525 16.1.2 register configuration.......................................................................................... 526 16.2 register descriptions ...................................................................................................... ... 526 16.2.1 system control register (syscr)....................................................................... 526 16.3 operation.................................................................................................................. .......... 527 16.4 usage note ................................................................................................................. ........ 527 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
xi section 17 rom .................................................................................................................... 529 17.1 overview................................................................................................................... ......... 529 17.1.1 block diagram...................................................................................................... 529 17.1.2 register configuration.......................................................................................... 530 17.2 register descriptions ...................................................................................................... ... 530 17.2.1 bus control register l (bcrl) ........................................................................... 530 17.3 operation.................................................................................................................. .......... 531 17.4 prom mode.................................................................................................................. .... 532 17.4.1 prom mode setting ............................................................................................ 532 17.4.2 socket adapter and memory map........................................................................ 532 17.5 programming................................................................................................................ ...... 535 17.5.1 overview............................................................................................................... 53 5 17.5.2 programming and verification ............................................................................. 535 17.5.3 programming precautions..................................................................................... 540 17.5.4 reliability of programmed data ........................................................................... 541 section 18 clock pulse generator ................................................................................... 543 18.1 overview................................................................................................................... ......... 543 18.1.1 block diagram...................................................................................................... 543 18.1.2 register configuration.......................................................................................... 543 18.2 register descriptions ...................................................................................................... ... 544 18.2.1 system clock control register (sckcr)............................................................ 544 18.3 oscillator................................................................................................................. ........... 545 18.3.1 connecting a crystal resonator............................................................................ 545 18.3.2 external clock input ............................................................................................. 547 18.4 duty adjustment circuit.................................................................................................... 549 18.5 medium-speed clock divider ........................................................................................... 549 18.6 bus master clock selection circuit................................................................................... 549 section 19 power-down modes ...................................................................................... 551 19.1 overview................................................................................................................... ......... 551 19.1.1 register configuration.......................................................................................... 552 19.2 register descriptions ...................................................................................................... ... 553 19.2.1 standby control register (sbycr) ..................................................................... 553 19.2.2 system clock control register (sckcr)............................................................ 554 19.2.3 module stop control register (mstpcr)........................................................... 555 19.3 medium-speed mode......................................................................................................... 5 56 19.4 sleep mode ................................................................................................................. ....... 557 19.5 module stop mode ........................................................................................................... . 557 19.5.1 module stop mode ............................................................................................... 557 19.5.2 usage notes .......................................................................................................... 558 19.6 software standby mode..................................................................................................... 5 59 19.6.1 software standby mode........................................................................................ 559 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
xii 19.6.2 clearing software standby mode......................................................................... 559 19.6.3 setting oscillation stabilization time after clearing software standby mode ... 560 19.6.4 software standby mode application example .................................................... 560 19.6.5 usage notes .......................................................................................................... 561 19.7 hardware standby mode ................................................................................................... 562 19.7.1 hardware standby mode ...................................................................................... 562 19.7.2 hardware standby mode timing.......................................................................... 562 19.8 ? clock output disabling function ................................................................................... 563 section 20 electrical characteristics .............................................................................. 565 20.1 absolute maximum ratings .............................................................................................. 565 20.2 dc characteristics ......................................................................................................... .... 566 20.3 ac characteristics ......................................................................................................... .... 573 20.3.1 clock timing ........................................................................................................ 574 20.3.2 control signal timing .......................................................................................... 576 20.3.3 bus timing ........................................................................................................... 578 20.3.4 timing of on-chip supporting modules.............................................................. 586 20.4 a/d conversion characteristics ........................................................................................ 591 20.5 d/a convervion characteristics ........................................................................................ 592 20.6 usage note ................................................................................................................. ........ 592 appendix a instruction set ............................................................................................... 593 a.1 instruction list ............................................................................................................ ....... 593 a.2 instruction codes ........................................................................................................... .... 617 a.3 operation code map.......................................................................................................... 632 a.4 number of states required for instruction execution....................................................... 636 a.5 bus states during instruction execution ........................................................................... 647 a.6 condition code modification ............................................................................................ 661 appendix b internal i/o register .................................................................................... 667 b.1 addresses ................................................................................................................... ........ 667 b.2 functions................................................................................................................... ......... 674 appendix c i/o port block diagrams ........................................................................... 781 c.1 port 1 block diagram ........................................................................................................ 781 c.2 port 2 block diagram ........................................................................................................ 783 c.3 port 3 block diagram ........................................................................................................ 787 c.4 port 4 block diagram ........................................................................................................ 790 c.5 port 5 block diagram ........................................................................................................ 791 c.6 port 6 block diagram ........................................................................................................ 795 c.7 port a block diagram........................................................................................................ 799 c.8 port b block diagram........................................................................................................ 802 c.9 port c block diagram........................................................................................................ 803 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
xiii c.10 port d block diagram....................................................................................................... . 804 c.11 port e block diagram....................................................................................................... . 805 c.12 port f block diagram ....................................................................................................... . 806 c.13 port g block diagram....................................................................................................... . 814 appendix d pin states ....................................................................................................... 817 d.1 port states in each mode ................................................................................................... 8 17 appendix e pin states at power-on .............................................................................. 821 e.1 when pins settle from an indeterminate state at power-on ............................................. 821 e.2 when pins settle from the high-impedance state at power-on ....................................... 822 appendix f timing of transition to and recovery from hardware standby mode ............................................................................................................... 823 appendix g product code lineup ................................................................................. 824 appendix h package dimensions .................................................................................. 825 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
1 section 1 overview 1.1 overview the h8s/2355 series is a series of microcomputers (mcus: microcomputer units), built around the h8s/2000 cpu, employing hitachi's proprietary architecture, and equipped with peripheral functions on-chip. the h8s/2000 cpu has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-mbyte linear address space. the instruction set is upward-compatible with h8/300 and h8/300h cpu instructions at the object-code level, facilitating migration from the h8/300, h8/300l, or h8/300h series. on-chip peripheral functions required for system configuration include data transfer controller (dtc) bus masters, rom and ram memory, a16-bit timer-pulse unit (tpu), 8-bit timer, watchdog timer (wdt), serial communication interface (sci), a/d converter, d/a converter* 1 , and i/o ports. the on-chip rom is either prom (ztat?* 2 ) or mask rom, with a capacity of 128, 64 or 32 kbytes. rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching has been speeded up, and processing speed increased. seven operating modes, modes 1 to 7, are provided, and there is a choice of address space and single-chip mode or external expansion mode. the features of the h8s/2355 series are shown in table 1-1. notes: 1. the h8s/2393 does not support a d/a converter. 2. ztat is a trademark of hitachi, ltd. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
2 table 1-1 overview item specification cpu general-register machine ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) high-speed operation suitable for realtime control ? maximum clock rate: 20 mhz ? high-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 16-bit register-register multiply : 1000 ns 32 16-bit register-register divide : 1000 ns instruction set suitable for high-speed operation ? sixty-five basic instructions ? 8/16/32-bit move/arithmetic and logic instructions ? unsigned/signed multiply and divide instructions ? powerful bit-manipulation instructions two cpu operating modes ? normal mode : 64-kbyte address space ? advanced mode : 16-mbyte address space bus controller address space divided into 8 areas, with bus specifications settable independently for each area chip select output possible for each area choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area number of program wait states can be set for each area burst rom directly connectable external bus release function data transfer controller (dtc) can be activated by internal interrupt or software multiple transfers or multiple types of transfer possible for one activation source transfer possible in repeat mode, block transfer mode, etc. request can be sent to cpu for interrupt that activated dtc 16-bit timer-pulse unit (tpu) 6-channel 16-bit timer on-chip pulse i/o processing capability for up to 16 pins' automatic 2-phase encoder count capability www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
3 item specification 8-bit timer 2 channels 8-bit up-counter (external event count capability) two time constant registers two-channel connection possible watchdog timer watchdog timer or interval timer selectable serial communication interface (sci) 3 channels asynchronous mode or synchronous mode selectable multiprocessor communication function smart card interface function a/d converter resolution: 10 bits input: 8 channels high-speed conversion: 6.7 s minimum conversion time (at 20 mhz operation) single or scan mode selectable sample and hold circuit a/d conversion can be activated by external trigger or timer trigger d/a converter * resolution: 8 bits output: 2 channels i/o ports 87 i/o pins, 8 input-only pins memory prom or mask rom high-speed static ram product name rom ram h8s/2355 128 kbytes 4 kbytes h8s/2353 64 kbytes 2 kbytes h8s/2393 32 kbytes 4 kbytes interrupt controller nine external interrupt pins (nmi, irq0 to irq7 ) 47 internal interrupt sources eight priority levels settable power-down state medium-speed mode sleep mode module stop mode software standby mode hardware standby mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
4 item specification operating seven mcu operating modes modes cpu external data bus mode operating mode description on-chip rom initial value maximum value 1 normal on-chip rom disabled expansion mode disabled 8 bits 16 bits 2 on-chip rom enabled expansion mode enabled 8 bits 16 bits 3 single-chip mode enabled 4 advanced on-chip rom disabled expansion mode disabled 16 bits 16 bits 5 on-chip rom disabled expansion mode disabled 8 bits 16 bits 6 on-chip rom enabled expansion mode enabled 8 bits 16 bits 7 single-chip mode enabled clock pulse generator built-in duty correction circuit packages 120-pin plastic tqfp (tfp-120) 128-pin plastic qfp (fp-128) product 5 v version 3.3 v version * 3 v version rom/ram lineup operating power supply voltage 5 v 10 % 3.0 v to 5.5 v 2.7 v to 5.5 v (bytes) operating frequency 2 to 20 mhz 2 to 13 mhz 2 to 10 mhz model name ztat? hd6472355f20 hd6472355te20 hd6472355f10 hd6472355te10 128 k/4 k mask rom hd6432355(a **) f hd6432355(a ** )te hd6432355(m ** )f hd6432355(m ** )te hd6432355(k ** )f hd6432355(k ** )te 128 k/4 k version hd6432353(a **) f hd6432353(a ** )te hd6432353(m ** )f hd6432353(m ** )te hd6432353(k ** )f hd6432353(k ** )te 64 k/2 k hd6432393(a **) f hd6432393(a ** )te hd6432393(m ** )f hd6432393(m ** )te hd6432393(k ** )f hd6432393(k ** )te 32 k/4 k packages fp-128 tfp-120 fp-128 tfp-120 fp-128 tfp-120 notes: 1. with the mask rom version, ( ** ) is the rom code. 2. please contact hitachi sales for information on the 3.3 v version. note: the h8s/2393 does not support a d/a converter. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
5 1.2 block diagram figure 1-1 and figure 1-2 show a internal block diagrams of the h8s/2355 and h8s/2353, and the h8s/2393. pe 7 /d 7 pe 6 /d 6 pe 5 /d 5 pe 4 /d 4 pe 3 /d 3 pe 2 /d 2 pe 1 /d 1 pe 0 /d 0 pd 7 /d 15 pd 6 /d 14 pd 5 /d 13 pd 4 /d 12 pd 3 /d 11 pd 2 /d 10 pd 1 /d 9 pd 0 /d 8 port d v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss v ss v ss v ss port a pa 7 /a 23 / irq7 pa 6 /a 22 / irq6 pa 5 /a 21 / irq5 pa 4 /a 20 / irq4 pa 3 /a 19 pa 2 /a 18 pa 1 /a 17 pa 0 /a 16 pb 7 /a 15 pb 6 /a 14 pb 5 /a 13 pb 4 /a 12 pb 3 /a 11 pb 2 /a 10 pb 1 /a 9 pb 0 /a 8 pc 7 /a 7 pc 6 /a 6 pc 5 /a 5 pc 4 /a 4 pc 3 /a 3 pc 2 /a 2 pc 1 /a 1 pc 0 /a 0 p3 5 / sck1 p3 4 / sck0 p3 3 / rxd1 p3 2 / rxd0 p3 1 / txd1 p3 0 / txd0 p5 0 / txd2 p5 1 / rxd2 p5 2 / sck2 p5 3 / adtrg p4 7 / an7/ da1 p4 6 / an6/ da0 p4 5 / an5 p4 4 / an4 p4 3 / an3 p4 2 / an2 p4 1 / an1 p4 0 / an0 v ref av cc av ss p2 0 / tioca3 p2 1 / tiocb3 p2 2 / tiocc 3/tmri0 p2 3 / tiocd 3/tmci0 p2 4 / tioca 4/tmri1 p2 5 / tiocb 4/tmci1 p2 6 / tioca 5/tmo0 p2 7 / tiocb 5/tmo1 p1 0 / tioca0 p1 1 / tiocb0 p1 2 / tiocc0 / tclka p1 3 / tiocd0 / tclkb p1 4 / tioca1 p1 5 / tiocb1 / tclkc p1 6 / tioca2 p1 7 / tiocb2 / tclkd p6 7 / cs7 / irq3 p6 6 / cs6 / irq2 p6 5 / irq1 p6 4 / irq0 p6 3 p6 2 p6 1 / cs5 p6 0 / cs4 pg 4 / cs0 pg 3 / cs1 pg 2 / cs2 pg 1 / cs3 pg 0 pf 7 / pf 6 / as pf 5 / rd pf 4 / hwr pf 3 / lwr pf 2 / wait pf 1 / back pf 0 / breq clock pulse generator rom ram wdt 8-bit timer tpu sci md 2 md 1 md 0 extal xtal stby res wdtovf nmi bus controller h8s/2000 cpu dtc interrupt controller port e internal data bus internal address bus port b port c port 3 port 5 port 4 port 2 port 1 port 6 port g port f peripheral data bus peripheral address bus d/a converter a/d converter figure 1-1 block diagram (h8s/2355, h8s/2353) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
6 pe 7 /d 7 pe 6 /d 6 pe 5 /d 5 pe 4 /d 4 pe 3 /d 3 pe 2 /d 2 pe 1 /d 1 pe 0 /d 0 internal data bus peripheral data bus peripheral address bus pd 7 /d 15 pd 6 /d 14 pd 5 /d 13 pd 4 /d 12 pd 3 /d 11 pd 2 /d 10 pd 1 /d 9 pd 0 /d 8 port d v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss pa 7 /a 23 / irq 7 pa 6 /a 22 / irq 6 pa 5 /a 21 / irq 5 pa 4 /a 20 / irq 4 pa 3 /a 19 pa 2 /a 18 pa 1 /a 17 pa 0 /a 16 pb 7 /a 15 pb 6 /a 14 pb 5 /a 13 pb 4 /a 12 pb 3 /a 11 pb 2 /a 10 pb 1 /a 9 pb 0 /a 8 pc 7 /a 7 pc 6 /a 6 pc 5 /a 5 pc 4 /a 4 pc 3 /a 3 pc 2 /a 2 pc 1 /a 1 pc 0 /a 0 p3 5 / sck1 p3 4 / sck0 p3 3 / rxd1 p3 2 / rxd0 p3 1 / txd1 p3 0 / txd0 p5 0 / txd2 p5 1 / rxd2 p5 2 / sck2 p5 3 / adtrg p4 7 / an7 p4 6 / an6 p4 5 / an5 p4 4 / an4 p4 3 / an3 p4 2 / an2 p4 1 / an1 p4 0 / an0 v ref av cc av ss p2 0 / tioca3 p2 1 / tiocb3 p2 2 / tiocc 3/tmri0 p2 3 / tiocd 3/tmci0 p2 4 / tioca 4/tmri1 p2 5 / tiocb 4/tmci1 p2 6 / tioca 5/tmo0 p2 7 / tiocb 5/tmo1 p1 0 / tioca0 p1 1 / tiocb0 p1 2 / tiocc0 / tclka p1 3 / tiocd0 / tclkb p1 4 / tioca1 p1 5 / tiocb1 / tclkc p1 6 / tioca2 p1 7 / tiocb2 / tclkd p6 7 / cs7 / irq3 p6 6 / cs6 / irq2 p6 5 / irq1 p6 4 / irq0 p6 3 p6 2 p6 1 / cs5 p6 0 / cs4 pg 4 / cs0 pg 3 / cs1 pg 2 / cs2 pg 1 / cs3 pg 0 pf 7 / pf 6 / as pf 5 /rd pf 4 / hwr pf 3 / lwr pf 2 / wait pf 1 / back pf 0 / breq rom port f clock pulse generator port g port a port b port c port 3 port 5 port 6 ram tpu md 2 md 1 md 0 extal xtal stby res wdtovf nmi h8s/2000 cpu dtc interrupt controller port e port 4 port 2 port 1 internal address bus bus controller sci wdt 8-bit timer a/d converter figure 1-2 block diagram (h8s/2393) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
7 1.3 pin description 1.3.1 pin arrangement figures 1-3 and 1-4 show the pin arrangement of the h8s/2355 and h8s/2353, and figure 1-5 and 1-6 show the pin arrangement of the h8s/2393. v cc pc 0 /a 0 pc 1 /a 1 pc 2 /a 2 pc 3 /a 3 v ss pc 4 /a 4 pc 5 /a 5 pc 6 /a 6 pc 7 /a 7 pb 0 /a 8 pb 1 /a 9 pb 2 /a 10 pb 3 /a 11 v ss pb 4 /a 12 pb 5 /a 13 pb 6 /a 14 pb 7 /a 15 pa 0 /a 16 pa 1 /a 17 pa 2 /a 18 pa 3 /a 19 v ss pa 4 /a 20 / irq4 pa 5 /a 21 / irq5 pa 6 /a 22 / irq6 pa 7 /a 23 / irq7 p6 7 / cs7/ irq3 p6 6 / cs6/ irq2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p5 1 /rxd2 p5 0 /txd2 pf 0 / breq pf 1 / back pf 2 / wait pf 3 / lwr pf 4 / hwr pf 5 /rd pf 6 /as v cc pf 7 / v ss extal xtal v cc stby nmi res wdtovf p2 0 / tioca3 p2 1 / tiocb3 p2 2 / tiocc3 /tmri0 p2 3 / tiocd3 /tmci0 p2 4 / tioca4 /tmri1 p2 5 / tiocb4 /tmci1 p2 6 / tioca5 /tmo0 p2 7 / tiocb5 /tmo1 p6 3 p6 2 p6 1 / cs5 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p5 2 /sck2 p5 3 / adtrg av cc v ref p4 0 / an0 p4 1 / an1 p4 2 / an2 p4 3 / an3 p4 4 / an4 p4 5 / an5 p4 6 / an6/ da0 p4 7 / an7/ da1 av ss v ss p1 7 / tiocb2 / tclkd p1 6 / tioca2 p1 5 / tiocb1 / tclkc p1 4 / tioca1 p1 3 / tiocd0 / tclkb p1 2 / tiocc0 / tclka p1 1 / tiocb0 p1 0 / tioca0 md 0 md 1 md 2 pg 0 pg 1 / cs3 pg 2 / cs2 pg 3 / cs1 pg 4 / cs0 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 p6 0 / cs4 v ss p3 5 / sck1 p3 4 / sck0 p3 3 / rxd1 p3 2 / rxd0 p3 1 / txd1 p3 0 / txd0 v cc pd 7 /d 15 pd 6 /d 14 pd 5 /d 13 pd 4 /d 12 v ss pd 3 /d 11 pd 2 /d 10 pd 1 /d 9 pd 0 /d 8 pe 7 /d 7 pe 6 /d 6 pe 5 /d 5 pe 4 /d 4 v ss pe 3 /d 3 pe 2 /d 2 pe 1 /d 1 pe 0 /d 0 v cc p6 4 / irq0 p6 5 / irq1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 figure 1-3 h8s/2355 and h8s/2353 pin arrangement (tfp-120: top view) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
8 pg 3 / cs1 pg 4 / cs0 v ss nc v cc pc 0 /a 0 pc 1 /a 1 pc 2 /a 2 pc 3 /a 3 v ss pc 4 /a 4 pc 5 /a 5 pc 6 /a 6 pc 7 /a 7 pb 0 /a 8 pb 1 /a 9 pb 2 /a 10 pb 3 /a 11 v ss pb 4 /a 12 pb 5 /a 13 pb 6 /a 14 pb 7 /a 15 pa 0 /a 16 pa 1 /a 17 pa 2 /a 18 pa 3 /a 19 v ss pa 4 /a 20 / irq4 pa 5 /a 21 / irq5 pa 6 /a 22 / irq6 pa 7 /a 23 / irq7 p6 7 / cs7/ irq3 p6 6 / cs6/ irq2 v ss v ss p6 5 / irq1 p6 4 / irq0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 p5 3 / adtrg p5 2 /sck2 v ss v ss p5 1 /rxd2 p5 0 /txd2 pf 0 / breq pf 1 / back pf 2 / wait pf 3 / lwr pf 4 / hwr pf 5 /rd pf 6 /as v cc pf 7 / v ss extal xtal v cc stby nmi res wdtovf p2 0 / tioca3 p2 1 / tiocb3 p2 2 / tiocc3 /tmri0 p2 3 / tiocd3 /tmci0 p2 4 / tioca4 /tmri1 p2 5 / tiocb4 /tmci1 p2 6 / tioca5 /tmo0 p2 7 / tiocb5 /tmo1 p6 3 p6 2 p6 1 / cs5 v ss v ss p6 0 / cs4 v ss 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p3 5 / sck1 p3 4 / sck0 p3 3 / rxd1 p3 2 / rxd0 p3 1 / txd1 p3 0 / txd0 v cc pd 7 /d 15 pd 6 /d 14 pd 5 /d 13 pd 4 /d 12 v ss pd 3 /d 11 pd 2 /d 10 pd 1 /d 9 pd 0 /d 8 pe 7 /d 7 pe 6 /d 6 pe 5 /d 5 pe 4 /d 4 v ss pe 3 /d 3 pe 2 /d 2 pe 1 /d 1 pe 0 /d 0 v cc av cc v ref p4 0 / an0 p4 1 / an1 p4 2 / an2 p4 3 / an3 p4 4 / an4 p4 5 / an5 p4 6 / an6/ da0 p4 7 / an7/ da1 av ss v ss p1 7 / tiocb2 / tclkd p1 6 / tioca2 p1 5 / tiocb1 / tclkc p1 4 / tioca1 p1 3 / tiocd0 / tclkb p1 2 / tiocc0 / tclka p1 1 / tiocb0 p1 0 / tioca0 md 0 md 1 md 2 pg 0 pg 1 / cs3 pg 2 / cs2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 figure 1-4 h8s/2355 and h8s/2353 pin arrangement (fp-128: top view) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
9 v cc pc 0 /a 0 pc 1 /a 1 pc 2 /a 2 pc 3 /a 3 v ss pc 4 /a 4 pc 5 /a 5 pc 6 /a 6 pc 7 /a 7 pb 0 /a 8 pb 1 /a 9 pb 2 /a 10 pb 3 /a 11 v ss pb 4 /a 12 pb 5 /a 13 pb 6 /a 14 pb 7 /a 15 pa 0 /a 16 pa 1 /a 17 pa 2 /a 18 pa 3 /a 19 v ss pa 4 /a 20 / irq4 pa 5 /a 21 / irq5 pa 6 /a 22 / irq6 pa 7 /a 23 / irq7 p6 7 / cs7 / irq3 p6 6 / cs6 / irq2 p5 2 / sck2 p5 3 / adtrg av cc v ref p4 0 / an0 p4 1 / an1 p4 2 / an2 p4 3 / an3 p4 4 / an4 p4 5 / an5 p4 6 / an6 p4 7 / an7 av ss v ss p1 7 / tiocb2 / tclkd p1 6 / tioca2 p1 5 / tiocb1 / tclkc p1 4 / tioca1 p1 3 / tiocd0 / tclkb p1 2 / tiocc0 / tclka p1 1 / tiocb0 p1 0 / tioca0 md 0 md 1 md 2 pg 0 pg 1 / cs3 pg 2 / cs2 pg 3 / cs1 pg 4 / cs0 p6 0 / cs4 v ss p3 5 / sck1 p3 4 / sck0 p3 3 / rxd1 p3 2 / rxd0 p3 1 / txd1 p3 0 / txd0 v cc pd 7 /d 15 pd 6 /d 14 pd 5 /d 13 pd 4 /d 12 v ss pd 3 /d 11 pd 2 /d 10 pd 1 /d 9 pd 0 /d 8 pe 7 /d 7 pe 6 /d 6 pe 5 /d 5 pe 4 /d 4 v ss pe 3 /d 3 pe 2 /d 2 pe 1 /d 1 pe 0 /d 0 v cc p6 4 / irq0 p6 5 / irq1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 p5 1 / rxd2 p5 0 / txd2 pf 0 / breq pf 1 / back pf 2 / wait pf 3 / lwr pf 4 / hwr pf 5 / rd pf 6 / as v cc pf 7 / v ss extal xtal v cc stby nmi res wdtovf p2 0 / tioca3 p2 1 / tiocb3 p2 2 / tiocc 3/tmri0 p2 3 / tiocd 3/tmci0 p2 4 / tioca 4/tmri1 p2 5 / tiocb 4/tmci1 p2 6 / tioca 5/tmo0 p2 7 / tiocb 5/tmo1 p6 3 p6 2 p6 1 / cs5 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 figure 1-5 h8s/2393 pin arrangement (tfp-120: top view) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
10 pg 3 / cs1 pg 4 / cs0 v ss nc v cc pc 0 /a 0 pc 1 /a 1 pc 2 /a 2 pc 3 /a 3 v ss pc 4 /a 4 pc 5 /a 5 pc 6 /a 6 pc 7 /a 7 pb 0 /a 8 pb 1 /a 9 pb 2 /a 10 pb 3 /a 11 v ss pb 4 /a 12 pb 5 /a 13 pb 6 /a 14 pb 7 /a 15 pa 0 /a 16 pa 1 /a 17 pa 2 /a 18 pa 3 /a 19 v ss pa 4 /a 20 / irq4 pa 5 /a 21 / irq5 pa 6 /a 22 / irq6 pa 7 /a 23 / irq7 p6 7 / cs7/ irq3 p6 6 / cs6/ irq2 v ss v ss p6 5 / irq1 p6 4 / irq0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 p5 3 / adtrg p5 2 / sck2 v ss v ss p5 1 / rxd2 p5 0 / txd2 pf 0 / breq pf 1 / back pf 2 / wait pf 3 / lwr pf 4 / hwr pf 5 / rd pf 6 / as v cc pf 7 / v ss extal xtal v cc stby nmi res wdtovf p2 0 / tioca3 p2 1 / tiocb3 p2 2 / tiocc 3/tmri0 p2 3 / tiocd 3/tmci0 p2 4 / tioca 4/tmri1 p2 5 / tiocb 4/tmci1 p2 6 / tioca 5/tmo0 p2 7 / tiocb 5/tmo1 p6 3 p6 2 p6 1 / cs5 v ss v ss p6 0 / cs4 v ss 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p3 5 / sck1 p3 4 / sck0 p3 3 / rxd1 p3 2 / rxd0 p3 1 / txd1 p3 0 / txd0 v cc pd 7 /d 15 pd 6 /d 14 pd 5 /d 13 pd 4 /d 12 v ss pd 3 /d 11 pd 2 /d 10 pd 1 /d 9 pd 0 /d 8 pe 7 /d 7 pe 6 /d 6 pe 5 /d 5 pe 4 /d 4 v ss pe 3 /d 3 pe 2 /d 2 pe 1 /d 1 pe 0 /d 0 v cc av cc v ref p4 0 / an0 p4 1 / an1 p4 2 / an2 p4 3 / an3 p4 4 / an4 p4 5 / an5 p4 6 / an6 p4 7 / an7 av ss v ss p1 7 / tiocb2 / tclkd p1 6 / tioca2 p1 5 / tiocb1 / tclkc p1 4 / tioca1 p1 3 / tiocd0 / tclkb p1 2 / tiocc0 / tclka p1 1 / tiocb0 p1 0 / tioca0 md 0 md 1 md 2 pg 0 pg 1 / cs3 pg 2 / cs2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 figure 1-6 h8s/2393 pin arrangement (fp-128: top view) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
11 1.3.2 pin functions in each operating mode table 1-2 shows the pin functions of the h8s/2355 series in each of the operating modes. table 1-2 pin functions in each operating mode pin no. pin name prom * 1 tfp-120 fp-128 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 mode 15v cc v cc v cc v cc v cc v cc v cc v cc 26a 0 pc 0 /a 0 pc 0 a 0 a 0 pc 0 /a 0 pc 0 a 0 37a 1 pc 1 /a 1 pc 1 a 1 a 1 pc 1 /a 1 pc 1 a 1 48a 2 pc 2 /a 2 pc 2 a 2 a 2 pc 2 /a 2 pc 2 a 2 59a 3 pc 3 /a 3 pc 3 a 3 a 3 pc 3 /a 3 pc 3 a 3 610v ss v ss v ss v ss v ss v ss v ss v ss 711a 4 pc 4 /a 4 pc 4 a 4 a 4 pc 4 /a 4 pc 4 a 4 812a 5 pc 5 /a 5 pc 5 a 5 a 5 pc 5 /a 5 pc 5 a 5 913a 6 pc 6 /a 6 pc 6 a 6 a 6 pc 6 /a 6 pc 6 a 6 10 14 a 7 pc 7 /a 7 pc 7 a 7 a 7 pc 7 /a 7 pc 7 a 7 11 15 a 8 pb 0 /a 8 pb 0 a 8 a 8 pb 0 /a 8 pb 0 a 8 12 16 a 9 pb 1 /a 9 pb 1 a 9 a 9 pb 1 /a 9 pb 1 oe 13 17 a 10 pb 2 /a 10 pb 2 a 10 a 10 pb 2 /a 10 pb 2 a 10 14 18 a 11 pb 3 /a 11 pb 3 a 11 a 11 pb 3 /a 11 pb 3 a 11 15 19 v ss v ss v ss v ss v ss v ss v ss v ss 16 20 a 12 pb 4 /a 12 pb 4 a 12 a 12 pb 4 /a 12 pb 4 a 12 17 21 a 13 pb 5 /a 13 pb 5 a 13 a 13 pb 5 /a 13 pb 5 a 13 18 22 a 14 pb 6 /a 14 pb 6 a 14 a 14 pb 6 /a 14 pb 6 a 14 19 23 a 15 pb 7 /a 15 pb 7 a 15 a 15 pb 7 /a 15 pb 7 a 15 20 24 pa 0 pa 0 pa 0 a 16 a 16 pa 0 /a 16 pa 0 a 16 21 25 pa 1 pa 1 pa 1 a 17 a 17 pa 1 /a 17 pa 1 v cc 22 26 pa 2 pa 2 pa 2 a 18 a 18 pa 2 /a 18 pa 2 v cc 23 27 pa 3 pa 3 pa 3 a 19 a 19 pa 3 /a 19 pa 3 nc 24 28 v ss v ss v ss v ss v ss v ss v ss v ss 25 29 pa 4 / irq4 pa 4 / irq4 pa 4 / irq4 a 20 a 20 pa 4 /a 20 / irq4 pa 4 / irq4 nc 26 30 pa 5 / irq5 pa 5 / irq5 pa 5 / irq5 pa 5 /a 21 / irq5 pa 5 /a 21 / irq5 pa 5 /a 21 / irq5 pa 5 / irq5 nc 27 31 pa 6 / irq6 pa 6 / irq6 pa 6 / irq6 pa 6 /a 22 / irq6 pa 6 /a 22 / irq6 pa 6 /a 22 / irq6 pa 6 / irq6 nc www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
12 pin no. pin name prom * 1 tfp-120 fp-128 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 mode 28 32 pa 7 / irq7 pa 7 / irq7 pa 7 / irq7 pa 7 /a 23 / irq7 pa 7 /a 23 / irq7 pa 7 /a 23 / irq7 pa 7 / irq7 nc 29 33 p6 7 / irq3 p6 7 / irq3 p6 7 / irq3 p6 7 / irq3 / cs7 p6 7 / irq3 / cs7 p6 7 / irq3 / cs 7 p6 7 / irq3 nc 30 34 p6 6 / irq2 p6 6 / irq2 p6 6 / irq2 p6 6 / irq2 / cs6 p6 6 / irq2 / cs6 p6 6 / irq2 / cs6 p6 6 / irq2 nc 35v ss v ss v ss v ss v ss v ss v ss v ss 36v ss v ss v ss v ss v ss v ss v ss v ss 31 37 p6 5 / irq1 p6 5 / irq1 p6 5 / irq1 p6 5 / irq1 p6 5 / irq1 p6 5 / irq1 p6 5 / irq1 nc 32 38 p6 4 / irq0 p6 4 / irq0 p6 4 / irq0 p6 4 / irq0 p6 4 / irq0 p6 4 / irq0 p6 4 / irq0 nc 33 39 v cc v cc v cc v cc v cc v cc v cc v cc 34 40 pe 0 /d 0 pe 0 /d 0 pe 0 pe 0 /d 0 pe 0 /d 0 pe 0 /d 0 pe 0 nc 35 41 pe 1 /d 1 pe 1 /d 1 pe 1 pe 1 /d 1 pe 1 /d 1 pe 1 /d 1 pe 1 nc 36 42 pe 2 /d 2 pe 2 /d 2 pe 2 pe 2 /d 2 pe 2 /d 2 pe 2 /d 2 pe 2 nc 37 43 pe 3 /d 3 pe 3 /d 3 pe 3 pe 3 /d 3 pe 3 /d 3 pe 3 /d 3 pe 3 nc 38 44 v ss v ss v ss v ss v ss v ss v ss v ss 39 45 pe 4 /d 4 pe 4 /d 4 pe 4 pe 4 /d 4 pe 4 /d 4 pe 4 /d 4 pe 4 nc 40 46 pe 5 /d 5 pe 5 /d 5 pe 5 pe 5 /d 5 pe 5 /d 5 pe 5 /d 5 pe 5 nc 41 47 pe 6 /d 6 pe 6 /d 6 pe 6 pe 6 /d 6 pe 6 /d 6 pe 6 /d 6 pe 6 nc 42 48 pe 7 /d 7 pe 7 /d 7 pe 7 pe 7 /d 7 pe 7 /d 7 pe 7 /d 7 pe 7 nc 43 49 d 8 d 8 pd 0 d 8 d 8 d 8 pd 0 d 0 44 50 d 9 d 9 pd 1 d 9 d 9 d 9 pd 1 d 1 45 51 d 10 d 10 pd 2 d 10 d 10 d 10 pd 2 d 2 46 52 d 11 d 11 pd 3 d 11 d 11 d 11 pd 3 d 3 47 53 v ss v ss v ss v ss v ss v ss v ss v ss 48 54 d 12 d 12 pd 4 d 12 d 12 d 12 pd 4 d 4 49 55 d 13 d 13 pd 5 d 13 d 13 d 13 pd 5 d 5 50 56 d 14 d 14 pd 6 d 14 d 14 d 14 pd 6 d 6 51 57 d 15 d 15 pd 7 d 15 d 15 d 15 pd 7 d 7 52 58 v cc v cc v cc v cc v cc v cc v cc v cc 53 59 p3 0 /txd0 p3 0 /txd0 p3 0 /txd0 p3 0 /txd0 p3 0 /txd0 p3 0 /txd0 p3 0 /txd0 nc 54 60 p3 1 /txd1 p3 1 /txd1 p3 1 /txd1 p3 1 /txd1 p3 1 /txd1 p3 1 /txd1 p3 1 /txd1 nc 55 61 p3 2 /rxd0 p3 2 /rxd0 p3 2 /rxd0 p3 2 /rxd0 p3 2 /rxd0 p3 2 /rxd0 p3 2 /rxd0 nc www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
13 pin no. pin name prom * 1 tfp-120 fp-128 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 mode 56 62 p3 3 /rxd1 p3 3 /rxd1 p3 3 /rxd1 p3 3 /rxd1 p3 3 /rxd1 p3 3 /rxd1 p3 3 /rxd1 nc 57 63 p3 4 /sck0 p3 4 /sck0 p3 4 /sck0 p3 4 /sck0 p3 4 /sck0 p3 4 /sck0 p3 4 /sck0 nc 58 64 p3 5 /sck1 p3 5 /sck1 p3 5 /sck1 p3 5 /sck1 p3 5 /sck1 p3 5 /sck1 p3 5 /sck1 nc 59 65 v ss v ss v ss v ss v ss v ss v ss v ss 60 66 p6 0 p6 0 p6 0 p6 0 / cs4 p6 0 / cs4 p6 0 / cs4 p6 0 nc 67v ss v ss v ss v ss v ss v ss v ss v ss 68v ss v ss v ss v ss v ss v ss v ss v ss 61 69 p6 1 p6 1 p6 1 p6 1 / cs5 p6 1 / cs5 p6 1 / cs5 p6 1 nc 62 70 p6 2 p6 2 p6 2 p6 2 p6 2 p6 2 p6 2 nc 63 71 p6 3 p6 3 p6 3 p6 3 p6 3 p6 3 p6 3 nc 64 72 p2 7 / tiocb5/ tmo1 p2 7 / tiocb5/ tmo1 p2 7 / tiocb5/ tmo1 p2 7 / tiocb5/ tmo1 p2 7 / tiocb5/ tmo1 p2 7 / tiocb5/ tmo1 p2 7 / tiocb5/ tmo1 nc 65 73 p2 6 / tioca5/ tmo0 p2 6 / tioca5/ tmo0 p2 6 / tioca5/ tmo0 p2 6 / tioca5/ tmo0 p2 6 / tioca5/ tmo0 p2 6 / tioca5/ tmo0 p2 6 / tioca5/ tmo0 nc 66 74 p2 5 / tiocb4/ tmci1 p2 5 / tiocb4/ tmci1 p2 5 / tiocb4/ tmci1 p2 5 / tiocb4/ tmci p2 5 / tiocb4/ tmci1 p2 5 / tiocb4/ tmci1 p2 5 / tiocb4/ tmci1 nc 67 75 p2 4 / tioca4/ tmri1 p2 4 / tioca4/ tmri1 p2 4 / tioca4/ tmri1 p2 4 / tioca4/ tmri1 p2 4 / tioca4/ tmri1 p2 4 / tioca4/ tmri1 p2 4 / tioca4/ tmri1 nc 68 76 p2 3 / tiocd3/ tmci0 p2 3 / tiocd3/ tmci0 p2 3 / tiocd3/ tmci0 p2 3 / tiocd3/ tmci0 p2 3 / tiocd3/ tmci0 p2 3 / tiocd3/ tmci0 p2 3 / tiocd3/ tmci0 nc 69 77 p2 2 / tiocc3/ tmri1 p2 2 / tiocc3/ tmri1 p2 2 / tiocc3/ tmri1 p2 2 / tiocc3/ tmri1 p2 2 / tiocc3/ tmri1 p2 2 / tiocc3/ tmri1 p2 2 / tiocc3/ tmri1 nc 70 78 p2 1 / tiocb3 p2 1 / tiocb3 p2 1 / tiocb3 p2 1 / tiocb3 p2 1 / tiocb3 p2 1 / tiocb3 p2 1 / tiocb3 nc 71 79 p2 0 / tioca3 p2 0 / tioca3 p2 0 / tioca3 p2 0 / tioca3 p2 0 / tioca3 p2 0 / tioca3 p2 0 / tioca3 nc 72 80 wdtovf wdtovf wdtovf wdtovf wdtovf wdtovf wdtovf nc 73 81 res res res res res res res v pp 74 82 nmi nmi nmi nmi nmi nmi nmi a 9 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
14 pin no. pin name prom * 1 tfp-120 fp-128 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 mode 75 83 stby stby stby stby stby stby stby v ss 76 84 v cc v cc v cc v cc v cc v cc v cc v cc 77 85 xtal xtal xtal xtal xtal xtal xtal nc 78 86 extal extal extal extal extal extal extal nc 79 87 v ss v ss v ss v ss v ss v ss v ss v ss 80 88 pf 7 /? pf 7 /? pf 7 /? pf 7 /? pf 7 /? pf 7 /? pf 7 /? nc 81 89 v cc v cc v cc v cc v cc v cc v cc v cc 82 90 as as pf 6 as as as pf 6 nc 83 91 rd rd pf 5 rd rd rd pf 5 nc 84 92 hwr hwr pf 4 hwr hwr hwr pf 4 nc 85 93 lwr lwr pf 3 lwr lwr lwr pf 3 nc 86 94 pf 2 / wait pf 2 / wait pf 2 pf 2 / wait pf 2 / wait pf 2 / wait pf 2 ce 87 95 pf 1 / back pf 1 / back pf 1 pf 1 / back pf 1 / back pf 1 / back pf 1 pgm 88 96 pf 0 / breq pf 0 / breq pf 0 pf 0 / breq pf 0 / breq pf 0 / breq pf 0 nc 89 97 p5 0 /txd2 p5 0 /txd 2 p5 0 /txd2 p5 0 /txd2 p5 0 /txd2 p5 0 /txd2 p5 0 /txd2 nc 90 98 p5 1 /rxd2 p5 1 /rxd2 p5 1 /rxd2 p5 1 /rxd2 p5 1 /rxd2 p5 1 /rxd2 p5 1 /rxd2 nc 99v ss v ss v ss v ss v ss v ss v ss v ss 100 v ss v ss v ss v ss v ss v ss v ss v ss 91 101 p5 2 /sck2 p5 2 /sck2 p5 2 /sck2 p5 2 /sck2 p5 2 /sck2 p5 2 /sck2 p5 2 /sck2 nc 92 102 p5 3 / adtrg p5 3 / adtrg p5 3 / adtrg p5 3 / adtrg p5 3 / adtrg p5 3 / adtrg p5 3 / adtrg nc 93 103 av cc av cc av cc av cc av cc av cc av cc v cc 94 104 v ref v ref v ref v ref v ref v ref v ref v cc 95 105 p4 0 /an0 p4 0 /an0 p4 0 /an0 p4 0 /an0 p4 0 /an0 p4 0 /an0 p4 0 /an0 nc 96 106 p4 1 /an1 p4 1 /an1 p4 1 /an1 p4 1 /an1 p4 1 /an1 p4 1 /an1 p4 1 /an1 nc 97 107 p4 2 /an2 p4 2 /an2 p4 2 /an2 p4 2 /an2 p4 2 /an2 p4 2 /an2 p4 2 /an2 nc 98 108 p4 3 /an3 p4 3 /an3 p4 3 /an3 p4 3 /an3 p4 3 /an3 p4 3 /an3 p4 3 /an3 nc 99 109 p4 4 /an4 p4 4 /an4 p4 4 /an4 p4 4 /an4 p4 4 /an4 p4 4 /an4 p4 4 /an4 nc 100 110 p4 5 /an5 p4 5 /an5 p4 5 /an5 p4 5 /an5 p4 5 /an5 p4 5 /an5 p4 5 /an5 nc 101 111 p4 6 /an6/ da0 * 2 p4 6 /an6/ da0 * 2 p4 6 /an6/ da0 * 2 p4 6 /an6/ da0 * 2 p4 6 /an6/ da0 * 2 p4 6 /an6/ da0 * 2 p4 6 /an6/ da0 * 2 nc 102 112 p4 7 /an7/ da1 * 2 p4 7 /an7/ da1 * 2 p4 7 /an7/ da1 * 2 p4 7 /an7/ da1 * 2 p4 7 /an7/ da1 * 2 p4 7 /an7/ da1 * 2 p4 7 /an7/ da1 * 2 nc 103 113 av ss av ss av ss av ss av ss av ss av ss v ss www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
15 pin no. pin name prom * 1 tfp-120 fp-128 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 mode 104 114 v ss v ss v ss v ss v ss v ss v ss v ss 105 115 p1 7 / tiocb2/ tclkd p1 7 / tiocb2/ tclkd p1 7 / tiocb2/ tclkd p1 7 / tiocb2/ tclkd p1 7 / tiocb2/ tclkd p1 7 / tiocb2/ tclkd p1 7 / tiocb2/ tclkd nc 106 116 p1 6 / tioca2 p1 6 / tioca2 p1 6 / tioca2 p1 6 / tioca2 p1 6 / tioca2 p1 6 / tioca2 p1 6 / tioca2 nc 107 117 p1 5 / tiocb1/ tclkc p1 5 / tiocb1/ tclkc p1 5 / tiocb1/ tclkc p1 5 / tiocb1/ tclkc p1 5 / tiocb1/ tclkc p1 5 / tiocb1/ tclkc p1 5 / tiocb1/ tclkc nc 108 118 p1 4 / tioca1 p1 4 / tioca1 p1 4 / tioca1 p1 4 / tioca1 p1 4 / tioca1 p1 4 / tioca1 p1 4 / tioca1 nc 109 119 p1 3 / tiocd0/ tclkb p1 3 / tiocd0/ tclkb p1 3 / tiocd0/ tclkb p1 3 / tiocd0/ tclkb p1 3 / tiocd0/ tclkb p1 3 / tiocd0/ tclkb p1 3 / tiocd0/ tclkb nc 110 120 p1 2 / tiocc0/ tclka p1 2 / tiocc0/ tclka p1 2 / tiocc0/ tclka p1 2 / tiocc0/ tclka p1 2 / tiocc0/ tclka p1 2 / tiocc0/ tclka p1 2 / tiocc0/ tclka nc 111 121 p1 1 / tiocb0 p1 1 / tiocb0 p1 1 / tiocb0 p1 1 / tiocb0 p1 1 / tiocb0 p1 1 / tiocb0 p1 1 / tiocb0 nc 112 122 p1 0 / tioca0 p1 0 / tioca0 p1 0 / tioca0 p1 0 / tioca0 p1 0 / tioca0 p1 0 / tioca0 p1 0 / tioca0 nc 113 123 md 0 md 0 md 0 md 0 md 0 md 0 md 0 v ss 114 124 md 1 md 1 md 1 md 1 md 1 md 1 md 1 v ss 115 125 md 2 md 2 md 2 md 2 md 2 md 2 md 2 v ss 116 126 pg 0 pg 0 pg 0 pg 0 pg 0 pg 0 pg 0 nc 117 127 pg 1 pg 1 pg 1 pg 1 / cs3 pg 1 / cs3 pg 1 / cs3 pg 1 nc 118 128 pg 2 pg 2 pg 2 pg 2 / cs2 pg 2 / cs2 pg 2 / cs2 pg 2 nc 119 1 pg 3 pg 3 pg 3 pg 3 / cs1 pg 3 / cs1 pg 3 / cs1 pg 3 nc 120 2 pg 4 / cs0 pg 4 / cs0 pg 4 pg 4 / cs0 pg 4 / cs0 pg 4 / cs0 pg 4 nc 3 v ss v ss v ss v ss v ss v ss v ss v ss 4 nc nc nc nc nc nc nc nc notes: nc pins should be connected to v ss or left open. 1. there is no prom version of the h8s/2393. 2. as the h8s/2393 does not support a d/a converter, it does not have the da0 and da1 outputs. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
16 1.3.3 pin functions table 1-3 outlines the pin functions of the h8s/2355 series. table 1-3 pin functions pin no. type symbol tfp-120 fp-128 i/o name and function power v cc 1, 33, 52, 76, 81 5, 39, 58, 84, 89 input power supply: for connection to the power supply. all v cc pins should be connected to the system power supply. v ss 6, 15, 24, 38, 47, 59, 79, 104 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100, 114 input ground: for connection to ground (0 v). all v ss pins should be connected to the system power supply (0 v). clock xtal 77 85 input connects to a crystal oscillator. see section 18, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. extal 78 86 input connects to a crystal oscillator. the extal pin can also input an external clock. see section 18, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. ? 80 88 output system clock: supplies the system clock to an external device. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
17 pin no. type symbol tfp-120 fp-128 i/o name and function operating mode control md 2 to md 0 115 to 113 125 to 123 input mode pins: these pins set the operating mode. the relation between the settings of pins md 2 to md 0 and the operating mode is shown below. these pins should not be changed while the h8s/2355 series is operating. md 2 md 1 md 0 operating mode 000 1 mode 1 1 0 mode 2 1 mode 3 1 0 0 mode 4 1 mode 5 1 0 mode 6 1 mode 7 system control res 73 81 input reset input: when this pin is driven low, the chip is reset. the type of reset can be selected according to the nmi input level. at power-on, the nmi pin input level should be set high. stby 75 83 input standby: when this pin is driven low, a transition is made to hardware standby mode. breq 88 96 input bus request: used by an external bus master to issue a bus request to the h8s/2355 series. back 87 95 output bus request acknowledge: indicates that the bus has been released to an external bus master. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
18 pin no. type symbol tfp-120 fp-128 i/o name and function interrupts nmi 74 82 input nonmaskable interrupt: requests a nonmaskable interrupt. when this pin is not used, it should be fixed high. irq7 to irq0 28 to 25, 29 to 32 32 to 29, 33, 34, 37, 38 input interrupt request 7 to 0: these pins request a maskable interrupt. address bus a 23 to a 0 28 to 25, 23 to 16, 14 to 7, 5 to 2 32 to 29, 27 to 20, 18 to 11, 9 to 6 output address bus: these pins output an address. data bus d 15 to d 0 51 to 48, 46 to 39, 37 to 34 57 to 54, 52 to 45, 43 to 40 i/o data bus: these pins constitute a bidirectional data bus. bus control cs7 to cs0 29, 30, 61, 60, 117 to 120 33, 34, 69, 66, 127, 128, 1, 2 output chip select: signals for selecting areas 7 to 0. as 82 90 output address strobe: when this pin is low, it indicates that address output on the address bus is enabled. rd 83 91 output read: when this pin is low, it indicates that the external address space can be read. hwr 84 92 output high write: a strobe signal that writes to external space and indicates that the upper half (d 15 to d 8 ) of the data bus is enabled. lwr 85 93 output low write: a strobe signal that writes to external space and indicates that the lower half (d 7 to d 0 ) of the data bus is enabled. wait 86 94 input wait: requests insertion of a wait state in the bus cycle when accessing external 3-state address space. lcas 86 94 output lower column address strobe: the 2- cas type (lcass = 0) dram lower column address strobe signal www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
19 pin no. type symbol tfp-120 fp-128 i/o name and function 16-bit timer- pulse unit (tpu) tclkd to tclka 105, 107, 109, 110 115, 117, 119, 120 input clock input d to a: these pins input an external clock. tioca0, tiocb0, tiocc0, tiocd0 112 to 109 122 to 119 i/o input capture/ output compare match a0 to d0: the tgr0a to tgr0d input capture input or output compare output, or pwm output pins. tioca1, tiocb1 108, 107 118, 117 i/o input capture/ output compare match a1 and b1: the tgr1a and tgr1b input capture input or output compare output, or pwm output pins. tioca2, tiocb2 106, 105 116, 115 i/o input capture/ output compare match a2 and b2: the tgr2a and tgr2b input capture input or output compare output, or pwm output pins. tioca3, tiocb3, tiocc3, tiocd3 71 to 68 79 to 76 i/o input capture/ output compare match a3 to d3: the tgr3a to tgr3d input capture input or output compare output, or pwm output pins. tioca4, tiocb4 67, 66 75, 74 i/o input capture/ output compare match a4 and b4: the tgr4a and tgr4b input capture input or output compare output, or pwm output pins. tioca5, tiocb5 65, 64 73, 72 i/o input capture/ output compare match a5 and b5: the tgr5a and tgr5b input capture input or output compare output, or pwm output pins. 8-bit timer tmo0, tmo1 65, 64 73, 72 output compare match output: the compare match output pins. tmci0, tmci1 68, 66 76, 74 input counter external clock input: input pins for the external clock input to the counter. tmri0, tmri1 69, 67 77, 75 input counter external reset input: the counter reset input pins. watchdog timer (wdt) wdtovf 72 80 output watchdog timer overflows: the counter overflows signal output pin in watchdog timer mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
20 pin no. type symbol tfp-120 fp-128 i/o name and function serial communication interface (sci) txd2, txd1, txd0 89, 54, 53 97, 60, 59 output transmit data (channel 0, 1, 2): data output pins. smart card interface rxd2, rxd1, rxd0 90, 56, 55 98, 62, 61 input receive data (channel 0, 1, 2): data input pins. sck2, sck1 sck0 91, 58 57 101, 64, 63 i/o serial clock (channel 0, 1, 2): clock i/o pins. a/d converter an7 to an0 102 to 95 112 to 105 input analog 7 to 0: analog input pins. adtrg 92 102 input a/d conversion external trigger input: pin for input of an external trigger to start a/d conversion. d/a converter * da1, da0 102, 101 112, 111 output analog output: d/a converter analog output pins. a/d converter and d/a converters av cc 93 103 input this is the power supply pin for the a/d converter and d/a converter. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+5 v). av ss 103 113 input this is the ground pin for the a/d converter and d/a converter. this pin should be connected to the system power supply (0 v). v ref 94 104 input this is the reference voltage input pin for the a/d converter and d/a converter. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+5 v). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
21 pin no. type symbol tfp-120 fp-128 i/o name and function i/o ports p1 7 to p1 0 105 to 112 115 to 122 i/o port 1: an 8-bit i/o port. input or output can be designated for each bit by means of the port 1 data direction register (p1ddr). p2 7 to p2 0 64 to 71 72 to 79 i/o port 2: an 8-bit i/o port. input or output can be designated for each bit by means of the port 2 data direction register (p2ddr). p3 5 to p3 0 58 to 53 64 to 59 i/o port 3: a 6-bit i/o port. input or output can be designated for each bit by means of the port 3 data direction register (p3ddr). p4 7 to p4 0 102 to 95 112 to 105 input port 4: an 8-bit input port. p5 3 to p5 0 92 to 89 102, 101, 98, 97 i/o port 5: a 4-bit i/o port. input or output can be designated for each bit by means of the port 5 data direction register (p5ddr). p6 7 to p6 0 29 to 32, 63 to 60 33, 34, 37, 38, 71 to 69, 66 i/o port 6: an 8-bit i/o port. input or output can be designated for each bit by means of the port 6 data direction register (p6ddr). pa 7 to pa 0 28 to 25, 23 to 20 32 to 29, 27 to 24 i/o port a: an 8-bit i/o port. input or output can be designated for each bit by means of the port a data direction register (paddr). pb 7 to pb 0 19 to 16, 14 to 11 23 to 20, 18 to 15 i/o port b: an 8-bit i/o port. input or output can be designated for each bit by means of the port b data direction register (pbddr). pc 7 to pc 0 10 to 7, 5 to 2 14 to 11, 9 to 6 i/o port c: an 8-bit i/o port. input or output can be designated for each bit by means of the port c data direction register (pcddr). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
22 pin no. type symbol tfp-120 fp-128 i/o name and function i/o ports pd 7 to pd 0 51 to 48, 46 to 43 57 to 54, 52 to 49 i/o port d: an 8-bit i/o port. input or output can be designated for each bit by means of the port d data direction register (pdddr). pe 7 to pe 0 42 to 39, 37 to 34 48 to 45, 43 to 40 i/o port e: an 8-bit i/o port. input or output can be designated for each bit by means of the port e data direction register (peddr). pf 7 to pf 0 80, 82 to 88 88, 90 to 96 i/o port f: an 8-bit i/o port. input or output can be designated for each bit by means of the port f data direction register (pfddr). pg 4 to pg 0 120 to 116 2, 1, 128 to 126 i/o port g: a 5-bit i/o port. input or output can be designated for each bit by means of the port g data direction register (pgddr). note: * the h8s/2393 does not support a d/a converter. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
23 section 2 cpu 2.1 overview the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte (architecturally 4-gbyte) linear address space, and is ideal for realtime control. 2.1.1 features the h8s/2000 cpu has the following features. upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h object programs general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) sixty-five basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @eern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes (4 gbytes architecturally) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
24 high-speed operation ? all frequently-used instructions execute in one or two states ? maximum clock rate : 20 mhz ? 8/16/32-bit register-register add/subtract : 50 ns ? 8 8-bit register-register multiply : 600 ns ? 16 ? 8-bit register-register divide : 600 ns ? 16 16-bit register-register multiply : 1000 ns ? 32 ? 16-bit register-register divide : 1000 ns two cpu operating modes ? normal mode ? advanced mode power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are as shown below. register configuration the mac register is supported only by the h8s/2600 cpu. basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. number of execution states the number of exection states of the mulxu and mulxs instructions. internal operation instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21 there are also differences in the address space, ccr and exr register functions, power-down state, etc., depending on the product. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
25 2.1.3 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements. more general registers and control registers ? eight 16-bit expanded registers, and one 8-bit control register, have been added. expanded address space ? normal mode supports the same 64-kbyte address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast. 2.1.4 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2000 cpu has the following enhancements. additional control register ? one 8-bit control register has been added. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
26 2.2 cpu operating modes the h8s/2000 cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space (architecturally a maximum 16-mbyte program area and a maximum of 4 gbytes for program and data areas combined). the mode is selected by the mode pins of the microcontroller. cpu operating modes normal mode advanced mode maximum 64 kbytes, program and data areas combined maximum 16-mbytes for program and data areas combined figure 2-1 cpu operating modes (1) normal mode the exception vector table and stack have the same structure as in the h8/300 cpu. address space: a maximum address space of 64 kbytes can be accessed. extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@Crn) or post-increment (@rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (en) will be affected. instruction set: all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
27 exception vector table and memory indirect branch addresses: in normal mode the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits. the configuration of the exception vector table in normal mode is shown in figure 2-2. for details of the exception vector table, see section 4, exception handling. h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b power-on reset exception vector manual reset exception vector exception vector 1 exception vector 2 exception vector table (reserved for system use) figure 2-2 exception vector table (normal mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16- bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
28 stack structure: when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (16 bits) exr * 1 reserved * 1, * 3 ccr ccr * 3 pc (16 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 figure 2-3 stack structure in normal mode (2) advanced mode address space: linear access is provided to a 16-mbyte maximum address space (architecturally a maximum 16-mbyte program area and a maximum 4-gbyte data area, with a maximum of 4 gbytes for program and data areas combined). extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. instruction set: all instructions and addressing modes can be used. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
29 exception vector table and memory indirect branch addresses: in advanced mode the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). for details of the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c exception vector table reserved power-on reset exception vector (reserved for system use) reserved exception vector 1 reserved manual reset exception vector h'00000010 h'00000008 h'00000007 figure 2-4 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
30 stack structure: in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (24 bits) exr * 1 reserved * 1, * 3 ccr pc (24 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 reserved figure 2-5 stack structure in advanced mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
31 2.3 address space figure 2-6 shows a memory map of the h8s/2000 cpu. the h8s/2000 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in advanced mode. (b) advanced mode h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff (a) normal mode data area program area cannot be used by the h8s/2355 series figure 2-6 memory map www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
32 2.4 register configuration 2.4.1 overview the cpu has the internal registers shown in figure 2-7. there are two types of registers: general registers and control registers. t i2 i1 i0 exr 76543210 pc 23 0 15 07 07 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend stack pointer program counter extended control register trace bit interrupt mask bits condition-code register interrupt mask bit user bit or interrupt mask bit * sp: pc: exr: t: i2 to i0: ccr: i: ui: note: * in the h8s/2355 series, this bit cannot be used as an interrupt mask. er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 76543210 half-carry flag user bit negative flag zero flag overflow flag carry flag h: u: n: z: v: c: figure 2-7 cpu registers www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
33 2.4.2 general registers the cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2-8 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2-8 usage of general registers www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
34 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2-9 shows the stack. free area stack area sp (er7) figure 2-9 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), and 8-bit condition-code register (ccr). (1) program counter (pc): this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) (2) extended control register (exr): this 8-bit register contains the trace bit (t) and three interrupt mask bits (i2 to i0). bit 7trace bit (t): selects trace mode. when this bit is cleared to 0, instructions are executed in sequence. when this bit is set to 1, a trace exception is generated each time an instruction is executed. bits 6 to 3reserved: these bits are reserved. they are always read as 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
35 bits 2 to 0interrupt mask bits (i2 to i0): these bits designate the interrupt mask level (0 to 7). for details, refer to section 5, interrupt controller. operations can be performed on the exr bits by the ldc, stc, andc, orc, and xorc instructions. all interrupts, including nmi, are disabled for three states after one of these instructions is executed, except for stc. (3) condition-code register (ccr): this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7interrupt mask bit (i): masks interrupts other than nmi when set to 1. (nmi is accepted regardless of the i bit setting.) the i bit is set to 1 by hardware at the start of an exception- handling sequence. for details, refer to section 5, interrupt controller. bit 6user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. with the h8s/2355 series, this bit cannot be used as an interrupt mask bit. bit 5half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3negative flag (n): stores the value of the most significant bit (sign bit) of data. bit 2zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
36 some instructions leave some or all of the flag bits unchanged. for the action of each instruction on the flag bits, refer to appendix a.1, list of instructions. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. 2.4.4 initial register values reset exception handling loads the cpu's program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets the interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
37 2.5 data formats the cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, , 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2-10 shows the data formats in general registers. 76543210 dont care 70 dont care 76543210 43 70 70 dont care upper lower lsb msb lsb data type register number data format 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data rnh rnl rnh rnl rnh rnl msb don? care upper lower 43 70 don? care 70 don? care 70 figure 2-10 general register data formats www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
38 0 msb lsb 15 word data word data rn en 0 lsb 15 16 msb 31 en rn general register er general register e general register r general register rh general register rl most significant bit least significant bit legend ern: en: rn: rnh: rnl: msb: lsb: 0 msb lsb 15 longword data ern data type register number data format figure 2-10 general register data formats (cont) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
39 2.5.2 memory data formats figure 2-11 shows the data formats in memory. the cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2-11 memory data formats when er7 is used as an address register to access the stack, the operand size should be word size or longword size. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
40 2.6 instruction set 2.6.1 overview the h8s/2000 cpu has 65 types of instructions. the instructions are classified by function in table 2-1. table 2-1 instruction classification function instructions size types data transfer mov bwl 5 pop * 1 , push * 1 wl ldm, stm l movfpe, movtpe * 3 b arithmetic add, sub, cmp, neg bwl 19 operations addx, subx, daa, das b inc, dec bwl adds, subs l mulxu, divxu, mulxs, divxs bw extu, exts wl tas b logic operations and, or, xor, not bwl 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr bwl 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 notes: b-byte size; w-word size; l-longword size. 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @- sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. bcc is the general name for conditional branch instructions. 3. cannot be used in the h8s/2355 series. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
41 2.6.2 instructions and addressing modes table 2-2 indicates the combinations of instructions and addressing modes that the h8s/2600 cpu can use. table 2-2 combinations of instructions and addressing modes addressing modes function data transfer arithmetic operations instruction mov bwl bwl bwl bwl bwl bwl b bwl bwl pop, push ?l ldm, stm ? add, cmp bwl bwl sub wlbwl addx, subx b b adds, subs l inc, dec bwl daa, das b neg ?wl extu, exts wl tas b note: * cannot be used in the h8s/2355 series. movfpe, b movtpe * mulxu, bw divxu mulxs, bw divxs #xx rn @ern @(d:16,ern) @(d:32,ern) @?rn/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
42 addressing modes function logic operations system control block data transfer shift bit manipulation branch instruction and, or, bwl bwl xor andc, b orc, xorc bcc, bsr jmp, jsr rts trapa rte sleep ldc b b wwww w w stc b wwww w w not ?wl ?wl ? b bb b nop ?w legend b: byte w: word l: longword #xx rn @ern @(d:16,ern) @(d:32,ern) @?rn/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
43 2.6.3 table of instructions classified by function table 2-3 summarizes the instructions in each functional category. the notation used in table 2-3 is defined below. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication division logical and logical or ? logical exclusive or ? move ? not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
44 table 2-3 instructions classified by function type instruction size * function data transfer mov b/w/l (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in the h8s/2355 series. movtpe b cannot be used in the h8s/2355 series. pop w/l @sp+ ? rn pops a register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn ? @Csp pushes a register onto the stack. push.w rn is identical to mov.w rn, @Csp. push.l ern is identical to mov.l ern, @Csp. ldm l @sp+ ? rn (register list) pops two or more general registers from the stack. stm l rn (register list) ? @Csp pushes two or more general registers onto the stack. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
45 type instruction size * function arithmetic operations add sub b/w/l rd rs ? rd, rd #imm ? rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 ? rd, rd 2 ? rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 ? rd, rd 2 ? rd, rd 4 ? rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust ? rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs ? rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. mulxs b/w rd rs ? rd performs signed multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. divxu b/w rd rs ? rd performs unsigned division on data in two general registers: either 16 bits 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits 16 bits ? 16-bit quotient and 16- bit remainder. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
46 type instruction size * function arithmetic operations divxs b/w rd rs ? rd performs signed division on data in two general registers: either 16 bits 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits 16 bits ? 16-bit quotient and 16- bit remainder. cmp b/w/l rd C rs, rd C #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 C rd ? rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas b @erd C 0, 1 ? ( of @erd) tests memory contents, and sets the most significant bit (bit 7) to 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
47 type instruction size * function logic operations and b/w/l rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) ? (rd) takes the one's complement of general register contents. shift operations shal shar b/w/l rd (shift) ? rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. shll shlr b/w/l rd (shift) ? rd performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. rotl rotr b/w/l rd (rotate) ? rd rotates general register contents. 1-bit or 2-bit rotation is possible. rotxl rotxr b/w/l rd (rotate) ? rd rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
48 type instruction size * function bit- manipulation instructions bset b 1 ? ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ? ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bnot b ? ( of ) ? ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ? ( of ) ? z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) ? c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) ? c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) ? c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) ? c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
49 type instruction size * function bit- manipulation instructions bxor bixor b b c ? ( of ) ? c exclusive-ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ? ( of ) ? c exclusive-ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) ? c transfers a specified bit in a general register or memory operand to the carry flag. ? ( of ) ? c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ? ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ? c ? ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
50 type instruction size * function branch instructions bcc branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear c = 0 (high or same) bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address. bsr branches to a subroutine at a specified address. jsr branches to a subroutine at a specified address. rts returns from a subroutine www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
51 type instruction size * function system control trapa starts trap-instruction exception handling. instructions rte returns from an exception-handling routine. sleep causes a transition to a power-down state. ldc b/w (eas) ? ccr, (eas) ? exr moves the source operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr ? (ead), exr ? (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ? ccr, exr #imm ? exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ? ccr, exr #imm ? exr logically ors the ccr or exr contents with immediate data. xorc b ccr ? #imm ? ccr, exr ? #imm ? exr logically exclusive-ors the ccr or exr contents with immediate data. nop pc + 2 ? pc only increments the program counter. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
52 type instruction size * function block data transfer instruction eepmov.b eepmov.w if r4l 1 0 then repeat @er5+ ? @er6+ r4lC1 ? r4l until r4l = 0 else next; if r4 1 0 then repeat @er5+ ? @er6+ r4C1 ? r4 until r4 = 0 else next; transfers a data block according to parameters set in general registers r4l or r4, er5, and er6. r4l or r4: size of block (bytes) er5: starting source address er6: starting destination address execution of the next instruction begins as soon as the transfer is completed. note: * size refers to the operand size. b: byte w: word l: longword www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
53 2.6.4 basic instruction formats the cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). figure 2-12 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc figure 2-12 instruction formats (examples) (1) operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. (2) register field: specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. (3) effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) condition field: specifies the branching condition of bcc instructions. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
54 2.7 addressing modes and effective address calculation 2.7.1 addressing mode the cpu supports the eight addressing modes listed in table 2-4. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2-4 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @Cern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 (1) register directrn: the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. (2) register indirect@ern: the register field of the instruction code specifies an address register (ern) which contains the address of the operand on memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). (3) register indirect with displacement@(d:16, ern) or @(d:32, ern): a 16-bit or 32-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
55 (4) register indirect with post-increment or pre-decrement@ern+ or @-ern: register indirect with post-increment?@ern+ the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. register indirect with pre-decrement?@-ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. (5) absolute address@aa:8, @aa:16, @aa:24, or @aa:32: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2-5 indicates the accessible absolute address ranges. table 2-5 absolute address access ranges absolute address normal mode advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
56 (6) immediate#xx:8, #xx:16, or #xx:32: the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative@(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is C126 to +128 bytes (C63 to +64 words) or C32766 to +32768 bytes (C16383 to +16384 words) from the branch instruction. the resulting value should be an even number. (8) memory indirect@@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h'0000ff in advanced mode). in normal mode the memory operand is a word operand and the branch address is 16 bits long. in advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (h'00). note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling. ( a ) normal mode ( b ) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address figure 2-13 branch address specification in memory indirect mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
57 if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (for further information, see section 2.5.2, memory data formats.) 2.7.2 effective address calculation table 2-6 indicates how effective addresses are calculated in each addressing mode. in normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
58 register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents. register indirect (@ern) 2 register indirect with displacement @(d:16, ern) or @(d:32, ern) 3 ? register indirect with pre-decrement @?rn 4 general register contents general register contents sign extension disp general register contents 1, 2, or 4 general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r r op disp 24 23 don? care 24 23 don? care 24 23 don? care 24 23 don? care table 2-6 effective address calculation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
59 5 @aa:8 absolute address @aa:16 @aa:32 6 immediate #xx:8/#xx:16/#xx:32 31 0 8 7 operand is immediate data. no. addressing mode and instruction format effective address calculation effective address (ea) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op imm h'ffff don? care 24 23 don? care 24 23 don? care 24 23 don? care sign extension www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
60 31 0 0 0 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 ? normal mode ? advanced mode 0 no. addressing mode and instruction format effective address calculation effective address (ea) 23 23 31 8 7 0 15 0 31 8 7 0 disp h'000000 abs h'000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs sign extension pc contents abs memory contents memory contents h'00 don? care 24 23 don? care don? care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
61 2.8 processing states 2.8.1 overview the cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. figure 2-14 shows a diagram of the processing states. figure 2-15 indicates the state transitions. reset state the cpu and all on-chip supporting modules have been initialized and are stopped. exception-handling state a transient state in which the cpu changes the normal processing flow in response to a reset, interrupt, or trap instruction. program execution state the cpu executes program instructions in sequence. bus-released state the external bus has been released in response to a bus request signal from a bus master other than the cpu. power-down state cpu operation is stopped to conserve power. * sleep mode software standby mode hardware standby mode processing states note: * the power-down state also includes a medium-speed mode, module stop mode etc. figure 2-14 processing states www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
62 end of bus request bus request program execution state bus-released state sleep mode exception-handling state external interrupt software standby mode res = high reset state stby = high, res = low hardware standby mode * 2 power-down state * 1 notes: 1. 2. from any state except hardware standby mode, a transition to the reset state occurs whenever res goes low. a transition can also be made to the reset state when the watchdog timer overflows. from an y state, a transition to hardware standb y mode occurs when stby g oes low. sleep instruction with ssby = 0 sleep instruction with ssby = 1 interrupt request end of bus request bus request request for exception handling end of exception handling figure 2-15 state transitions 2.8.2 reset state when the res input goes low all current processing stops and the cpu enters the reset state. the cpu enters the power-on reset state when the nmi pin is high, or the manual reset state when the nmi pin is low. all interrupts are masked in the reset state. reset exception handling starts when the res signal changes from low to high. the reset state can also be entered by a watchdog timer overflow. for details, refer to section 11, watchdog timer. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
63 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to a reset, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. (1) types of exception handling and their priority exception handling is performed for traces, resets, interrupts, and trap instructions. table 2-7 indicates the types of exception handling and their priority. trap instruction exception handling is always accepted, in the program execution state. exception handling and the stack structure depend on the interrupt control mode set in syscr. table 2-7 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. trace end of instruction execution or end of exception-handling sequence * 1 when the trace (t) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence interrupt end of instruction execution or end of exception-handling sequence * 2 when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed * 3 notes: 1. traces are enabled only in interrupt control mode 2. trace exception-handling is not executed at the end of the rte instruction. 2. interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. 3. trap instruction exception handling is always accepted, in the program execution state. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
64 (2) reset exception handling after the res pin has gone low and the reset state has been entered, when res goes high again, reset exception handling starts. the cpu enters the power-on reset state when the nmi pin is high, or the manual reset state when the nmi pin is low. when reset exception handling starts the cpu fetches a start address (vector) from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during reset exception handling and after it ends. (3) traces traces are enabled only in interrupt control mode 2. trace mode is entered when the t bit of exr is set to 1. when trace mode is established, trace exception handling starts at the end of each instruction. at the end of a trace exception-handling sequence, the t bit of exr is cleared to 0 and trace mode is cleared. interrupt masks are not affected. the t bit saved on the stack retains its value of 1, and when the rte instruction is executed to return from the trace exception-handling routine, trace mode is entered again. trace exception- handling is not executed at the end of the rte instruction. trace mode is not entered in interrupt control mode 0, regardless of the state of the t bit. (4) interrupt exception handling and trap instruction exception handling when interrupt or trap-instruction exception handling begins, the cpu references the stack pointer (er7) and pushes the program counter and other control registers onto the stack. next, the cpu alters the settings of the interrupt mask bits in the control registers. then the cpu fetches a start address (vector) from the exception vector table and program execution starts from that start address. figure 2-16 shows the stack after exception handling ends. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
65 (c) interrupt control mode 0 (d) interrupt control mode 2 ccr pc (24 bits) sp note: * ignored when returning. ccr pc (24 bits) sp exr reserved * (a) interrupt control mode 0 (b) interrupt control mode 2 ccr ccr * pc (16 bits) sp ccr ccr * pc (16 bits) sp exr reserved * normal mode advanced mode figure 2-16 stack structure after exception handling (examples) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
66 2.8.4 program execution state in this state the cpu executes program instructions in sequence. 2.8.5 bus-released state this is a state in which the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. there is one other bus master in addition to the cpu: the data transfer controller (dtc). for further details, refer to section 6, bus controller. 2.8.6 power-down state the power-down state includes both modes in which the cpu stops operating and modes in which the cpu does not stop. there are three modes in which the cpu stops operating: sleep mode, software standby mode, and hardware standby mode. there are also two other power-down modes: medium-speed mode, and module stop mode. in medium-speed mode the cpu and other bus masters operate on a medium-speed clock. module stop mode permits halting of the operation of individual modules, other than the cpu. for details, refer to section 19, power-down state. (1) sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the software standby bit (ssby) in the standby control register (sbycr) is cleared to 0. in sleep mode, cpu operations stop immediately after execution of the sleep instruction. the contents of cpu registers are retained. (2) software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit in sbycr is set to 1. in software standby mode, the cpu and clock halt and all mcu operations stop. as long as a specified voltage is supplied, the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. (3) hardware standby mode: a transition to hardware standby mode is made when the stby pin goes low. in hardware standby mode, the cpu and clock halt and all mcu operations stop. the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
67 2.9 basic timing 2.9.1 overview the cpu is driven by a system clock, denoted by the symbol ?. the period from one rising edge of ? to the next is referred to as a "state." the memory cycle or bus cycle consists of one, two, or three states. different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 on-chip memory (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 2-17 shows the on-chip memory access cycle. figure 2-18 shows the pin states. internal address bus internal read signal internal data bus internal write signal internal data bus ? bus cycle t1 address read data write data read access write access figure 2-17 on-chip memory access cycle www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
68 bus cycle t1 unchanged address bus as rd hwr , lwr data bus ? high high high hi g h-impedance state figure 2-18 pin states during on-chip memory access www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
69 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. figure 2-19 shows the access timing for the on-chip supporting modules. figure 2-20 shows the pin states. bus cycle t1 t2 address read data write data internal read signal internal data bus internal write signal internal data bus read access write access internal address bus ? figure 2-19 on-chip supporting module access cycle www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
70 bus cycle t1 t2 unchanged address bus as rd hwr , lwr data bus ? high high high high-impedance state figure 2-20 pin states during on-chip supporting module access 2.9.4 external address space access timing the external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. in three-state access, wait states can be inserted. for further details, refer to section 6, bus controller. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
71 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8s/2355 series has seven operating modes (modes 1 to 7). these modes enable selection of the cpu operating mode, enabling/disabling of on-chip rom, and the initial bus width setting, by setting the mode pins (md 2 to md 0 ). table 3-1 lists the mcu operating modes. table 3-1 mcu operating mode selection mcu cpu external data bus operating mode md 2 md 1 md 0 operating mode description on-chip rom initial width max. width 0 000 1 1 normal on-chip rom disabled, expanded mode disabled 8 bits 16 bits 2 1 0 on-chip rom enabled, expanded mode enabled 8 bits 16 bits 3 1 single-chip mode 4 1 0 0 advanced on-chip rom disabled, expanded mode disabled 16 bits 16 bits 5 1 8 bits 16 bits 6 1 0 on-chip rom enabled, expanded mode enabled 8 bits 16 bits 7 1 single-chip mode the cpu's architecture allows for 4 gbytes of address space, but the h8s/2355 series actually accesses a maximum of 16 mbytes. modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the external expansion modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
72 note that the functions of each pin depend on the operating mode. the h8s/2355 series can be used only in modes 1 to 7. this means that the mode pins must be set to select one of these modes. do not change the inputs at the mode pins during operation. 3.1.2 register configuration the h8s/2355 series has a mode control register (mdcr) that indicates the inputs at the mode pins (md 2 to md 0 ), and a system control register (syscr) that controls the operation of the h8s/2355 series. table 3-2 summarizes these registers. table 3-2 mcu registers name abbreviation r/w initial value address * mode control register mdcr r undetermined h'ff3b system control register syscr r/w h'01 h'ff39 note: * lower 16 bits of the address. 3.2 register descriptions 3.2.1 mode control register (mdcr) 7 1 6 0 5 0 4 0 3 0 0 mds0 * r 2 mds2 * r 1 mds1 * r note: * determined by pins md 2 to md 0 . bit initial value r/w : : : mdcr is an 8-bit read-only register that indicates the current operating mode of the h8s/2355 series. bit 7reserved: read-only bit, always read as 1. bits 6 to 3reserved: read-only bits, always read as 0. bits 2 to 0mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md 2 to md 0 (the current operating mode). bits mds2 to mds0 correspond to md 2 to md 0 . mds2 to mds0 are read-only bits-they cannot be written to. the mode pin (md 2 to md 0 ) input levels are latched into these bits when mdcr is read. these latches are canceled by a power-on reset, but are retained after a manual reset. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
73 3.2.2 system control register (syscr) 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 0 1 0 r/w bit initial value r/w : : : bit 7reserved: only 0 should be written to this bit. bit 6reserved: read-only bit, always read as 0. bits 5 and 4interrupt control mode 1 and 0 (intm1, intm0): these bits select the control mode of the interrupt controller. for details of the interrupt control modes, see section 5.4.1, interrupt control modes and interrupt operation. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 control of interrupts by i bit (initial value) 1 setting prohibited 1 0 2 control of interrupts by i2 to i0 bits and ipr 1 setting prohibited bit 3nmi edge select (nmieg): selects the valid edge of the nmi interrupt input. bit 3 nmieg description 0 an interrupt is requested at the falling edge of nmi input (initial value) 1 an interrupt is requested at the rising edge of nmi input bit 2reserved: read-only bit, always read as 0. bit 1reserved: only 0 should be written to this bit. bit 0ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset status is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
74 3.3 operating mode descriptions 3.3.1 mode 1 the cpu can access a 64-kbyte address space in normal mode. the on-chip rom is disabled, and 8-bit bus mode is set, immediately after a reset. ports b and c function as an address bus, port d functions as a data bus, and part of port f carries bus control signals. however, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port e becomes a data bus. 3.3.2 mode 2 the cpu can access a 64-kbyte address space in normal mode. the on-chip rom is enabled, and 8-bit bus mode is set. immediately after a reset. ports b and c function as input ports immediately after a reset. they can each be set to output addresses by setting the corresponding bits in the data direction register (ddr) to 1. port d functions as a data bus, and part of port f carries bus control signals. however, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port e becomes a data bus. the amount of on-chip rom that can be used is limited to 56 kbytes. 3.3.3 mode 3 the cpu can access a 64-kbyte address space in normal mode. the on-chip rom is enabled, but external addresses cannot be accessed. all i/o ports are available for use as input-output ports. the amount of on-chip rom that can be used is limited to 56 kbytes. 3.3.4 mode 4 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. ports a, b and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. however, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
75 3.3.5 mode 5 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. ports a, b and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port e becomes a data bus. 3.3.6 mode 6 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. ports a, b and c function as input ports immediately after a reset. they can each be set to output addresses by setting the corresponding bits in the data direction register (ddr) to 1. port d functions as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port e becomes a data bus. 3.3.7 mode 7 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, but external addresses cannot be accessed. all i/o ports are available for use as input-output ports. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
76 3.4 pin functions in each operating mode the pin functions of ports a to f vary depending on the operating mode. table 3-3 shows their functions in each operating mode. table 3-3 pin functions in each mode port mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port a pa 7 to pa 5 pppp * /a p * /a p * /a p pa 4 to pa 0 aa port b a p * /apaap * /a p port c a p * /apaap * /a p port d d d p dddp port e p * /d p * /d p p/d p * /d p * /d p port f pf 7 p/c * p/c * p * /c p/c * p/c * p/c * p * /c pf 6 to pf 3 ccpcccp pf 2 to pf 0 p * /c p * /c p * /c p * /c p * /c legend p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : after reset 3.5 memory map in each operating mode a memory map of the h8s/2355 is shown in figure 3.1, a memory map of the h8s/2353 in figure 3.2, and a memory map of the h8s/2393 in figure 3.3. the address space is 64 kbytes in modes 1 to 3 (normal modes), and 16 mbytes in modes 4 to 7 (advanced modes). the on-chip rom capacity of the h8s/2355 is 128 kbytes, but only 56 kbytes are available in modes 2 and 3 (normal modes). the address space is divided into eight areas for modes 4 to 7. for details, see section 6, bus controller. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
77 mode 1 (normal expanded mode with on-chip rom disabled) mode 2 (normal expanded mode with on-chip rom enabled) mode 3 (normal single-chip mode) external address space on-chip rom on-chip ram * note: * external addresses can be accessed by clearing the rame bit in syscr to 0. internal i/o registers on-chip rom external address space external address space on-chip ram * on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space h'0000 h'0000 h'0000 h'dfff h'e000 h'ec00 h'fc00 h'fe40 h'fe40 h'ffff h'ec00 h'fc00 h'ffff h'ec00 h'fbff h'ffff h'ff08 h'ff08 h'fe40 h'ff07 h'ff28 h'ff28 h'ff28 figure 3-1 memory map in each operating mode in the h8s/2355 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
78 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom on-chip ram * 3 notes: internal i/o registers on-chip rom external address space external address space on-chip ram * 3 on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space h'000000 h'000000 h'000000 h'020000 h'ffec00 h'fffc00 h'fffe40 h'fffe40 h'ffffff h'ffec00 h'fffc00 h'ffffff h'01ffff h'ffec00 h'fffbff h'ffffff h'ffff08 h'ffff08 h'fffe40 h'ffff07 h'ffff28 h'ffff28 h'ffff28 on-chip rom/ external address space * 1 on-chip rom/ reserved area * 2 h'010000 h'010000 when the eae bit in bcrl is set to 1, this area is external address space. when the eae bit is cleared to 0, it is on-chip rom. this area is reserved when the eae bit in bcrl is set to 1, and on-chip rom when the eae bit is cleared to 0. external addresses can be accessed by clearing the rame bit in syscr to 0. 1. 2. 3. figure 3-1 memory map in each operating mode in the h8s/2355 (cont) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
79 mode 1 (normal expanded mode with on-chip rom disabled) mode 2 (normal expanded mode with on-chip rom enabled) mode 3 (normal single-chip mode) external address space on-chip rom on-chip ram * note: * external addresses can be accessed by clearing the rame bit in syscr to 0. internal i/o registers on-chip rom external address space external address space on-chip ram * reserved area reserved area on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space h'0000 h'0000 h'0000 h'dfff h'e000 h'ec00 h'f400 h'fc00 h'ffff h'ec00 h'f400 h'f400 h'fc00 h'ffff h'fbff h'ffff h'fe40 h'ff08 h'fe40 h'ff08 h'fe40 h'ff07 h'ff28 h'ff28 h'ff28 figure 3-2 memory map in each operating mode in the h8s/2353 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
80 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom on-chip ram * 2 notes: internal i/o registers on-chip rom external address space external address space on-chip ram * 2 reserved area reserved area on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space h'000000 h'000000 h'000000 h'020000 h'ffec00 h'fff400 h'fff400 h'fffc00 h'ffffff h'ffec00 h'fffc00 h'ffffff h'fffbff h'fff400 h'ffffff h'ffff08 h'ffff08 h'fffe40 h'ffff07 h'ffff28 h'ffff28 h'ffff28 external address space/reserved area * 1 h'fffe40 h'fffe40 h'010000 h'00ffff when the eae bit in bcrl is set to 1, this area is external address space. when the eae bit is cleared to 0, it is on-chip rom. external addresses can be accessed by clearing the rame bit in syscr to 0. 1. 2. figure 3-2 memory map in each operating mode in the h8s/2353 (cont) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
81 h'0000 h'ec00 h'fc00 h'ffff h'e000 h'0000 h'ec00 h'fc00 h'0000 h'ec00 h'fbff on-chip ram * 2 on-chip ram * 2 on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space external address space external address space external address space h'fe40 h'ff08 h'ff28 h'ffff h'fe40 h'ff08 h'ff28 h'ffff h'fe40 h'ff07 h'ff28 h'8000 h'dfff h'7fff reserved area h'7fff h'fbff h'fbff mode 1 (normal expanded mode with on-chip rom disabled) mode 2 (normal expanded mode with on-chip rom enabled) mode 3 (normal single-chip mode) external address space on-chip rom on-chip rom notes: when the eae bit in bcrl is set to 1, this area is external address space. when the eae bit is cleared to 0, it is on-chip rom. external addresses can be accessed by clearing the rame bit in syscr to 0. 1. 2. figure 3-3 memory map in each operating mode in the h8s/2393 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
82 h'000000 h'ffec00 h'fffc00 h'01ffff h'020000 h'000000 h'ffec00 h'fffc00 h'000000 h'ffec00 h'fffbff h'ffffff h'fffe40 h'ffff08 h'ffff28 h'ffffff h'fffe40 h'ffff08 h'ffff28 h'ffffff h'fffe40 h'ffff07 h'ffff28 h'007fff h'007fff h'010000 h'008000 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom reserved area on-chip rom external address space/reserved area * 1 on-chip ram * 2 notes: internal i/o registers external address space external address space on-chip ram * 2 on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space when the eae bit in bcrl is set to 1, this area is external address space. when the eae bit is cleared to 0, it is on-chip rom. external addresses can be accessed by clearing the rame bit in syscr to 0. 1. 2. figure 3-3 memory map in each operating mode in the h8s/2393 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
83 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. exception handling is prioritized as shown in table 4-1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exceptions are accepted at all times, in the program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits of syscr. table 4-1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. the cpu enters the power-on reset state when the nmi pin is high, or the manual reset state when the nmi pin is low. trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 low trap instruction (trapa) * 3 started by execution of a trap instruction (trapa) notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in program execution state. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
84 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows: 1. the program counter (pc), condition code register (ccr), and extended register (exr) are pushed onto the stack. 2. the interrupt mask bits are updated. the t bit is cleared to 0. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out. 4.1.3 exception vector table the exception sources are classified as shown in figure 4-1. different vector addresses are assigned to different exception sources. table 4-2 lists the exception sources and their vector addresses. exception sources reset trace interrupts trap instruction power-on reset manual reset external interrupts: nmi, irq7 to irq0 internal interrupts: 47 interrupt sources in on-chip supporting modules figure 4-1 exception sources in modes 6 and 7 in the h8s/2355, the on-chip rom available for use after a power-on reset is the 64-kbyte area comprising addresses h'000000 to h'00ffff. care is required when setting vector addresses. in this case, clearing the eae bit in bcrl enables the 128-kbyte area comprising addresses h'000000 to h'01ffff to be used. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
85 table 4-2 exception vector table vector address * 1 exception source vector number normal mode advanced mode power-on reset 0 h'0000 to h'0001 h'0000 to h'0003 manual reset 1 h'0002 to h'0003 h'0004 to h'0007 reserved for system use 2 h'0004 to h'0006 h'0008 to h'000b 3 h'0006 to h'0007 h'000c to h'000f 4 h'0008 to h'0009 h'0010 to h'0013 trace 5 h'000a to h'000b h'0014 to h'0017 reserved for system use 6 h'000c to h'000d h'0018 to h'001b external interrupt nmi 7 h'000e to h'000f h'001c to h'001f trap instruction (4 sources) 8 h'0010 to h'0011 h'0020 to h'0023 9 h'0012 to h'0013 h'0024 to h'0027 10 h'0014 to h'0015 h'0028 to h'002b 11 h'0016 to h'0017 h'002c to h'002f reserved for system use 12 h'0018 to h'0019 h'0030 to h'0033 13 h'001a to h'001b h'0034 to h'0037 14 h'001c to h'001d h'0038 to h'003b 15 h'001e to h'001f h'003c to h'003f external interrupt irq0 16 h'0020 to h'0021 h'0040 to h'0043 irq1 17 h'0022 to h'0023 h'0044 to h'0047 irq2 18 h'0024 to h'0025 h'0048 to h'004b irq3 19 h'0026 to h'0027 h'004c to h'004f irq4 20 h'0028 to h'0029 h'0050 to h'0053 irq5 21 h'002a to h'002b h'0054 to h'0057 irq6 22 h'002c to h'002d h'0058 to h'005b irq7 23 h'002e to h'002f h'005c to h'005f internal interrupt * 2 24 ? 91 h'0030 to h'0031 ? h'00b6 to h'00b7 h'0060 to h'0063 ? h'016c to h'016f notes: 1. lower 16 bits of the address. 2. for details of internal interrupt vectors, see section 5.3.3, interrupt exception handling vector table. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
86 4.2 reset 4.2.1 overview a reset has the highest exception priority. when the res pin goes low, all processing halts and the h8s/2355 series enters the reset state. a reset initializes the internal state of the cpu and the registers of on-chip supporting modules. immediately after a reset, interrupt control mode 0 is set. reset exception handling begins when the res pin changes from low to high. the level of the nmi pin at reset determines whether the type of reset is a power-on reset or a manual reset. the h8s/2355 series can also be reset by overflow of the watchdog timer. for details see section 11, watchdog timer. 4.2.2 reset types a reset can be of either of two types: a power-on reset or a manual reset. reset types are shown in table 4-3. a power-on reset should be used when powering on. the internal state of the cpu is initialized by either type of reset. a power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and i/o ports, which retain their previous states. with a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module i/o pins are switched to i/o ports controlled by ddr and dr. table 4-3 reset types reset transition conditions internal state type nmi res cpu on-chip supporting modules power-on reset high low initialized initialized manual reset low low initialized initialized, except for bus controller and i/o ports a reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
87 4.2.3 reset sequence the h8s/2355 series enters the reset state when the res pin goes low. to ensure that the h8s/2355 series is reset, hold the res pin low for at least 20 ms at power-up. to reset the h8s/2355 series during operation, hold the res pin low for at least 20 states. when the res pin goes high after being held low for the necessary time, the h8s/2355 series starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, the t bit is cleared to 0 in exr, and the i bit is set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figures 4-2 and 4-3 show examples of the reset sequence. internal address bus internal read signal internal write signal internal data bus (1) (3) vector fetch internal processing prefetch of first program instruction high (1) reset exception handling vector address ((1) = h'0000) (2) start address (contents of reset exception handling vector address) (3) start address ((3) = (2)) (4) first program instruction (2) (4) ? res figure 4-2 reset sequence (modes 2 and 3) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
88 address bus vector fetch internal processing prefetch of first program instruction (1) (3) reset exception handling vector address ((1) = h'000000, (3) = h'000002) (2) (4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2) (4)) (6) first program instruction ? res (1) (5) high (2) (4) (3) (6) rd hwr , lwr d 15 to d 0 * note: * 3 program wait states are inserted. ** figure 4-3 reset sequence (mode 4) 4.2.4 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 4.2.5 state of on-chip supporting modules after reset release after reset release, mstpcr is initialized to h'3fff and all modules except the dtc enter module stop mode. consequently, on-chip supporting module registers cannot be read or written to. register reading and writing is enabled when module stop mode is exited. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
89 4.3 traces traces are enabled in interrupt control mode 2. trace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. for details of interrupt control modes, see section 5, interrupt controller. if the t bit in exr is set to 1, trace mode is activated. in trace mode, a trace exception occurs on completion of each instruction. trace mode is canceled by clearing the t bit in exr to 0. it is not affected by interrupt masking. table 4-4 shows the state of ccr and exr after execution of trace exception handling. interrupts are accepted even within the trace exception handling routine. the t bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the rte instruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. table 4-4 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 trace exception handling cannot be used. 210 legend 1: set to 1 0: cleared to 0 : retains value prior to execution. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
90 4.4 interrupts interrupt exception handling can be requested by nine external sources (nmi, irq7 to irq0) and 47 internal sources in the on-chip supporting modules. figure 4-4 classifies the interrupt sources and the number of interrupts of each type. the on-chip supporting modules that can request interrupts include the watchdog timer (wdt), 16-bit timer-pulse unit (tpu), 8-bit timer, serial communication interface (sci), data transfer controller (dtc), and a/d converter. each interrupt source has a separate vector address. nmi is the highest-priority interrupt. interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiplexed interrupt control. for details of interrupts, see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq7 to irq0 (8) wdt * 1 (1) tpu (26) 8-bit timer (6) sci (12) dtc (1) a/d converter (1) numbers in parentheses are the numbers of interrupt sources. 1. when the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. notes: figure 4-4 interrupt sources and number of interrupts www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
91 4.5 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4-5 shows the status of ccr and exr after execution of trap instruction exception handling. table 4-5 status of ccr and exr after trap instruction exception handling ccr exr interrupt control mode i ui i2 to i0 t 01 210 legend 1: set to 1 0: cleared to 0 : retains value prior to execution. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
92 4.6 stack status after exception handling figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. sp sp ccr ccr * pc (16 bits) ccr ccr * pc (16 bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * ignored on return. figure 4-5 (1) stack status after exception handling (normal modes) sp sp ccr pc (24bits) ccr pc (24bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * ignored on return. figure 4-5 (2) stack status after exception handling (advanced modes) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
93 4.7 notes on use of the stack when accessing word data or longword data, the h8s/2355 series assumes that the lowest address bit is 0. the stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (sp, er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4-6 shows an example of what happens when the sp value is odd. sp legend note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. sp sp ccr pc r1l pc h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff mov.b r1l, @Cer7 sp set to h'fffeff trap instruction executed data saved above sp contents of ccr lost ccr: condition code register pc: program counter r1l: general register r1l sp: stack pointer figure 4-6 operation when sp value is odd www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
95 section 5 interrupt controller 5.1 overview 5.1.1 features the h8s/2355 series controls interrupts by means of an interrupt controller. the interrupt controller has the following features: two interrupt control modes ? any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). priorities settable with ipr ? an interrupt priority register (ipr) is provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. ? nmi is assigned the highest priority level of 8, and can be accepted at all times. independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. nine external interrupts ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. ? falling edge, rising edge, or both edge detection, or level sensing, can be selected for irq7 to irq0. dtc control ? dtc activation is performed by means of interrupts. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
96 5.1.2 block diagram a block diagram of the interrupt controller is shown in figure 5-1. syscr nmi input irq input internal interrupt request wovi to tei intm1 intm0 nmieg nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i, ui i2 to i0 ccr exr cpu iscr ier isr ipr syscr : irq sense control register : irq enable register : irq status register : interrupt priority register : system control register legend figure 5-1 block diagram of interrupt controller www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
97 5.1.3 pin configuration table 5-1 summarizes the pins of the interrupt controller. table 5-1 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 7 to 0 irq7 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 5.1.4 register configuration table 5-2 summarizes the registers of the interrupt controller. table 5-2 interrupt controller registers name abbreviation r/w initial value address * 1 system control register syscr r/w h'01 h'ff39 irq sense control register h iscrh r/w h'00 h'ff2c irq sense control register l iscrl r/w h'00 h'ff2d irq enable register ier r/w h'00 h'ff2e irq status register isr r/(w) * 2 h'00 h'ff2f interrupt priority register a ipra r/w h'77 h'fec4 interrupt priority register b iprb r/w h'77 h'fec5 interrupt priority register c iprc r/w h'77 h'fec6 interrupt priority register d iprd r/w h'77 h'fec7 interrupt priority register e ipre r/w h'77 h'fec8 interrupt priority register f iprf r/w h'77 h'fec9 interrupt priority register g iprg r/w h'77 h'feca interrupt priority register h iprh r/w h'77 h'fecb interrupt priority register i ipri r/w h'77 h'fecc interrupt priority register j iprj r/w h'77 h'fecd interrupt priority register k iprk r/w h'77 h'fece notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
98 5.2 register descriptions 5.2.1 system control register (syscr) 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 0 1 0 r/w bit initial value r/w : : : syscr is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for nmi. only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, system control register (syscr). syscr is initialized to h'01 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 5 and 4interrupt control mode 1 and 0 (intm1, intm0): these bits select one of two interrupt control modes for the interrupt controller. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 interrupts are controlled by i bit (initial value) 1 setting prohibited 1 0 2 interrupts are controlled by bits i2 to i0, and ipr 1 setting prohibited bit 3nmi edge select (nmieg): selects the input edge for the nmi pin. bit 3 nmieg description 0 interrupt request generated at falling edge of nmi input (initial value) 1 interrupt request generated at rising edge of nmi input www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
99 5.2.2 interrupt priority registers a to k (ipra to iprk) 7 0 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 0 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w bit initial value r/w : : : the ipr registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between ipr settings and interrupt sources is shown in table 5-3. the ipr registers set a priority (level 7 to 0) for each interrupt source other than nmi. the ipr registers are initialized to h'77 by a reset and in hardware standby mode. bits 7 and 3reserved: read-only bits, always read as 0. table 5-3 correspondence between interrupt sources and ipr settings bits register 6 to 4 2 to 0 ipra irq0 irq1 iprb irq2 irq3 irq4 irq5 iprc irq6 irq7 dtc iprd watchdog timer * ipre * a/d converter iprf tpu channel 0 tpu channel 1 iprg tpu channel 2 tpu channel 3 iprh tpu channel 4 tpu channel 5 ipri 8-bit timer channel 0 8-bit timer channel 1 iprj * sci channel 0 iprk sci channel 1 sci channel 2 note: * reserved bits. these bits cannot be modified and are always read as 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
100 as shown in table 5-3, multiple interrupts are assigned to one ipr. setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. the lowest priority level, level 0, is assigned by setting h'0, and the highest priority level, level 7, by setting h'7. when interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the ipr registers is selected. this interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (i2 to i0) in the extend register (exr) in the cpu, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the cpu. 5.2.3 irq enable register (ier) ier is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests irq7 to irq0. 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value r/w : : : ier is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 0irq7 to irq0 enable (irq7e to irq0e): these bits select whether irq7 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupts disabled (initial value) 1 irqn interrupts enabled (n = 7 to 0) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
101 5.2.4 irq sense control registers h and l (iscrh, iscrl) iscrh 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value r/w : : : iscrl 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value r/w : : : the iscr registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins irq7 to irq0 . the iscr registers are initialized to h'0000 by a reset and in hardware standby mode. bits 15 to 0: irq7 sense control a and b (irq7sca, irq7scb) to irq0 sense control a and b (irq0sca, irq0scb) bits 15 to 0 irq7scb to irq0scb irq7sca to irq0sca description 0 0 interrupt request generated at irq7 to irq0 input low level (initial value) 1 interrupt request generated at falling edge of irq7 to irq0 input 1 0 interrupt request generated at rising edge of irq7 to irq0 input 1 interrupt request generated at both falling and rising edges of irq7 to irq0 input www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
102 5.2.5 irq status register (isr) 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value r/w note: * only 0 can be written, to clear the flag. : : : isr is an 8-bit readable/writable register that indicates the status of irq7 to irq0 interrupt requests. isr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 0irq7 to irq0 flags (irq7f to irq0f): these bits indicate the status of irq7 to irq0 interrupt requests. bit n irqnf description 0 [clearing conditions] (initial value) cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set (irqnscb = 1 or irqnsca = 1) when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 1 [setting conditions] when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 7 to 0) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
103 5.3 interrupt sources interrupt sources comprise external interrupts (nmi and irq7 to irq0) and internal interrupts (47 sources). 5.3.1 external interrupts there are nine external interrupts: nmi and irq7 to irq0. of these, nmi and irq2 to irq0 can be used to restore the h8s/2355 series from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 7. irq7 to irq0 interrupts: interrupts irq7 to irq0 are requested by an input signal at pins irq7 to irq0 . interrupts irq7 to irq0 have the following features: using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq7 to irq0 . enabling or disabling of interrupt requests irq7 to irq0 can be selected with ier. the interrupt priority level can be set with ipr. the status of interrupt requests irq7 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. a block diagram of interrupts irq7 to irq0 is shown in figure 5-2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: n: 7 to 0 figure 5-2 block diagram of interrupts irq7 to irq0 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
104 figure 5-3 shows the timing of setting irqnf. ? irqn input pin irqnf figure 5-3 timing of setting irqnf the vector numbers for irq7 to irq0 interrupt exception handling are 23 to 16. detection of irq7 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0 and use the pin as an i/o pin for another function. 5.3.2 internal interrupts there are 47 sources for internal interrupts from on-chip supporting modules. for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. the interrupt priority level can be set by means of ipr. the dtc can be activated by a tpu, 8-bit timer, sci, or other interrupt request. when the dtc is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 interrupt exception handling vector table table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by means of the ipr. the situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5-4. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
105 table 5-4 interrupt sources, vector addresses, and interrupt priorities origin of vector address * interrupt source interrupt source vector number normal mode advanced mode ipr priority nmi external 7 h'000e h'001c high irq0 pin 16 h'0020 h'0040 ipra6 to 4 irq1 17 h'0022 h'0044 ipra2 to 0 irq2 irq3 18 19 h'0024 h'0026 h'0048 h'004c iprb6 to 4 irq4 irq5 20 21 h'0028 h'002a h'0050 h'0054 iprb2 to 0 irq6 irq7 22 23 h'002c h'002e h'0058 h'005c iprc6 to 4 swdtend (software activation interrupt end) dtc 24 h'0030 h'0060 iprc2 to 0 wovi (interval timer) watchdog timer 25 h'0032 h'0064 iprd6 to 4 reserved 26 27 h'0034 h'0036 h'0068 h'006c adi (a/d conversion end) a/d 28 h'0038 h'0070 ipre2 to 0 reserved 29 30 31 h'003a h'003c h'003e h'0074 h'0078 h'007c tgi0a (tgr0a input capture/compare match) tgi0b (tgr0b input capture/compare match) tgi0c (tgr0c input capture/compare match) tgi0d (tgr0d input capture/compare match) tci0v (overflow 0) tpu channel 0 32 33 34 35 36 h'0040 h'0042 h'0044 h'0046 h'0048 h'0080 h'0084 h'0088 h'008c h'0090 iprf6 to 4 reserved 37 38 39 h'004a h'004c h'004e h'0094 h'0098 h'009c low www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
106 vector address * interrupt source vector number normal mode advanced mode ipr priority tgi1a (tgr1a input capture/compare match) tgi1b (tgr1b input capture/compare match) tci1v (overflow 1) tci1u (underflow 1) tpu channel 1 40 41 42 43 h'0050 h'0052 h'0054 h'0056 h'00a0 h'00a4 h'00a8 h'00ac iprf2 to 0 high tgi2a (tgr2a input capture/compare match) tgi2b (tgr2b input capture/compare match) tci2v (overflow 2) tci2u (underflow 2) tpu channel 2 44 45 46 47 h'0058 h'005a h'005c h'005e h'00b0 h'00b4 h'00b8 h'00bc iprg6 to 4 tgi3a (tgr3a input capture/compare match) tgi3b (tgr3b input capture/compare match) tgi3c (tgr3c input capture/compare match) tgi3d (tgr3d input capture/compare match) tci3v (overflow 1) tpu channel 3 48 49 50 51 52 h'0060 h'0062 h'0064 h'0066 h'0068 h'00c0 h'00c4 h'00c8 h'00cc h'00d0 iprg2 to 0 reserved 53 54 55 h'006a h'006c h'006e h'00d4 h'00d8 h'00dc tgi4a (tgr4a input capture/compare match) tgi4b (tgr4b input capture/compare match) tci4v (overflow 4) tci4u (underflow 4) tpu channel 4 56 57 58 59 h'0070 h'0072 h'0074 h'0076 h'00e0 h'00e4 h'00e8 h'00ec iprh6 to 4 tgi5a (tgr5a input capture/compare match) tgi5b (tgr5b input capture/compare match) tci5v (overflow 5) tci5u (underflow 5) tpu channel 5 60 61 62 63 h'0078 h'007a h'007c h'007e h'00f0 h'00f4 h'00f8 h'00fc iprh2 to 0 low origin of interrupt source www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
107 vector address * interrupt source vector number normal mode advanced mode ipr priority cmia0 (compare match a0) cmib0 (compare match b0) ovi0 (overflow 0) 8-bit timer channel 0 64 65 66 h'0080 h'0082 h'0084 h'0100 h'0104 h'0108 ipri6 to 4 high reserved 67 h'0086 h'010c cmia1 (compare match a1) cmib1 (compare match b1) ovi1 (overflow 1) 8-bit timer channel 1 68 69 70 h'0088 h'008a h'008c h'0110 h'0114 h'0118 ipri2 to 0 reserved 71 72 73 74 75 76 77 78 79 h'008e h'0090 h'0092 h'0094 h'0096 h'0098 h'009a h'009c h'009e h'011c h'0120 h'0124 h'0128 h'012c h'0130 h'0134 h'0138 h'013c eri0 (receive error 0) rxi0 (reception completed 0) txi0 (transmit data empty 0) tei0 (transmission end 0) sci channel 0 80 81 82 83 h'00a0 h'00a2 h'00a4 h'00a6 h'0140 h'0144 h'0148 h'014c iprj2 to 0 eri1 (receive error 1) rxi1 (reception completed 1) txi1 (transmit data empty 1) tei1 (transmission end 1) sci channel 1 84 85 86 87 h'00a8 h'00aa h'00ac h'00ae h'0150 h'0154 h'0158 h'015c iprk6 to 4 eri2 (receive error 2) rxi2 (reception completed 2) txi2 (transmit data empty 2) tei2 (transmission end 2) sci channel 2 88 89 90 91 h'00b0 h'00b2 h'00b4 h'00b6 h'0160 h'0164 h'0168 h'016c iprk2 to 0 low note: * lower 16 bits of the start address. origin of interrupt source www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
108 5.4 interrupt operation 5.4.1 interrupt control modes and interrupt operation interrupt operations in the h8s/2355 series differ depending on the interrupt control mode. nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 5-5 shows the interrupt control modes. the interrupt controller performs interrupt control according to the interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in ipr, and the masking state indicated by the i and ui bits in the cpus ccr, and bits i2 to i0 in exr. table 5-5 interrupt control modes interrupt syscr priority setting interrupt control mode intm1 intm0 registers mask bits description 0 0 0 i interrupt mask control is performed by the i bit. 1 setting prohibited 2 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. 1 setting prohibited www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
109 figure 5-4 shows a block diagram of the priority decision circuit. interrupt acceptance control 8-level mask control default priority determination vector number interrupt control mode 2 ipr interrupt source i2 to i0 interrupt control mode 0 i figure 5-4 block diagram of interrupt control operation (1) interrupt acceptance control in interrupt control mode 0, interrupt acceptance is controlled by the i bit in ccr. table 5-6 shows the interrupts selected in each interrupt control mode. table 5-6 interrupts selected in each interrupt control mode (1) interrupt mask bits interrupt control mode i selected interrupts 0 0 all interrupts 1 nmi interrupts 2 * all interrupts legend * : don't care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
110 (2) 8-level control in interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (ipr). the interrupt source selected is the interrupt with the highest priority level, and whose priority level set in ipr is higher than the mask level. table 5-7 interrupts selected in each interrupt control mode (2) interrupt control mode selected interrupts 0 all interrupts 2 highest-priority-level (ipr) interrupt whose priority level is greater than the mask level (ipr > i2 to i0). (3) default priority determination when an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. if the same value is set for ipr, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accepted interrupt source are held pending. table 5-8 shows operations and control signal functions in each interrupt control mode. table 5-8 operations and control signal functions in each interrupt control mode setting interrupt acceptance control 8-level control t intm1 intm0 i i2 to i0 ipr (trace) 000 im x * 2 210x * 1 im pr t legend : interrupt operation control performed x : no operation. (all interrupts enabled) im : used as interrupt mask bit pr : sets priority. : not used. notes: 1. set to 1 when interrupt is accepted. 2. keep the initial setting. interrupt control mode default priority determination www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
111 5.4.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in the cpus ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] the i bit is then referenced. if the i bit is cleared to 0, the interrupt request is accepted. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. [3] interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] next, the i bit in ccr is set to 1. this masks all interrupts except nmi. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
112 program execution status interrupt generated? nmi irq0 irq1 tei2 i=0 save pc and ccr i ? 1 read vector address branch to interrupt handling routine yes no yes yes yes no no no yes yes no hold pending figure 5-5 flowchart of procedure up to interrupt acceptance in interrupt control mode 0 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
113 5.4.3 interrupt control mode 2 eight-level masking is implemented for irq interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits i2 to i0 of exr in the cpu with ipr. figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc, ccr, and exr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the interrupt mask level is set to h'7. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
114 yes program execution status interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine hold pending level 1 interrupt? mask level 0 yes yes no yes yes yes no yes yes no no no no no no figure 5-6 flowchart of procedure up to interrupt acceptance in interrupt control mode 2 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
115 5.4.4 interrupt exception handling sequence figure 5-7 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
116 (14) (12) (10) (8) (6) (4) (2) (1) (5) (7) (9) (11) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data us ? (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp-2 sp-4 saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10) (12)) first instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) figure 5-7 interrupt exception handling www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
117 5.4.5 interrupt response times the h8s/2355 series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip rom and the stack area in on-chip ram, enabling high- speed processing. table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5-9 are explained in table 5-10. table 5-9 interrupt response times normal mode advanced mode no. execution status intm1 = 0 intm1 = 1 intm1 = 0 intm1 = 1 1 interrupt priority determination * 1 33 33 2 number of wait states until executing instruction ends * 2 1 to 19+2s i 1 to 19+2s i 1 to 19+2s i 1 to 19+2s i 3 pc, ccr, exr stack save 2s k 3s k 2s k 3s k 4 vector fetch s i s i 2s i 2s i 5 instruction fetch * 3 2s i 2s i 2s i 2s i 6 internal processing * 4 22 22 total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. table 5-10 number of states in interrupt handling routine execution statuses object of access external device 8 bit bus 16 bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6+2m 2 3+m branch address read s j stack manipulation s k legend m : number of wait states in an external device access. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
118 5.5 usage notes 5.5.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared. figure 5-8 shows and example in which the cmiea bit in 8-bit timer tcr is cleared to 0. internal address bus internal write signal ? cmiea cmfa cmia interrupt signal tcr write cycle by cpu cmia exception handling tcr address figure 5-8 contention between interrupt generation and disabling the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
119 5.5.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 times when interrupts are disabled there are times when interrupt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt acceptance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction. 5.5.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
120 5.6 dtc activation by interrupt 5.6.1 overview the dtc can be activated by an interrupt. in this case, the following options are available: interrupt request to cpu activation request to dtc selection of a number of the above for details of interrupt requests that can be used with to activate the dtc, see section 7, data transfer controller. 5.6.2 block diagram figure 5-9 shows a block diagram of the dtc interrupt controller. selection circuit dtcer dtvecr control logic determination of priority cpu dtc dtc activation request vector number clear signal cpu interrupt request vector number select signal interrupt request interrupt source clear signal irq interrupt on-chip supporting module clear signal interrupt controller i, i2 to i0 swdte clear signal figure 5-9 interrupt control for dtc and dmac www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
121 5.6.3 operation the interrupt controller has three main functions in dtc control. (1) selection of interrupt source: interrupt sources can be specified as dtc activation requests or cpu interrupt requests by means of the dtce bit of dtcea to dtcef in the dtc. after a dtc data transfer, the dtce bit can be cleared to 0 and an interrupt request sent to the cpu in accordance with the specification of the disel bit of mrb in the dtc. when the dtc has performed the specified number of data transfers and the transfer counter value is zero, the dtce bit is cleared to 0 and an interrupt request is sent to the cpu after the dtc data transfer. (2) determination of priority: the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. see section 7.3.3, dtc vector table, for the respective priorities. (3) operation order: if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. if the same interrupt is selected as a dtc activation source or cpu interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the dtce bit of dtcea to dtcef in the dtc and the disel bit of mrb in the dtc. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
122 table 5-11 interrupt source selection and clearing control settings dtc interrupt source selection/clearing control dtce disel dtc cpu 0 * x d 10 d x 1 d legend d : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt handling routine.) : the relevant interrupt is used. the interrupt source is not cleared. x : the relevant bit cannot be used. * : don't care (4) notes on use: sci and a/d converter interrupt sources are cleared when the dtc reads or writes to the prescribed register, and are not dependent upon the disel bit. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
123 section 6 bus controller 6.1 overview the h8s/2355 series has a built-in bus controller (bsc) that manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu and data transfer controller (dtc). 6.1.1 features the features of the bus controller are listed below. manages external address space in area units ? in advanced mode, manages the external space as 8 areas of 2-mbytes ? in normal mode, manages the external space as a single area ? bus specifications can be set independently for each area basic bus interface ? chip select ( cs0 to cs7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? 2-state access or 3-state access can be selected for each area ? program wait states can be inserted for each area burst rom interface ? burst rom interface can be set for area 0 ? choice of 1- or 2-state burst access idle cycle insertion ? an idle cycle can be inserted in case of an external read cycle between different areas ? an idle cycle can be inserted in case of an external write cycle immediately after an external read cycle bus arbitration function ? includes a bus arbiter that arbitrates bus mastership among the cpu and dtc other features ? external bus release function www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
124 6.1.2 block diagram figure 6-1 shows a block diagram of the bus controller. area decoder bus controller abwcr astcr bcrh bcrl internal address bus cs0 to cs7 external bus control signals breq back internal control signals wait controller wcrh wcrl bus mode signal bus arbiter cpu bus request signal dtc bus request signal cpu bus acknowledge signal dtc bus acknowledge signal wait internal data bus figure 6-1 block diagram of bus controller www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
125 6.1.3 pin configuration table 6-1 summarizes the pins of the bus controller. table 6-1 bus controller pins name symbol i/o function address strobe as output strobe signal indicating that address output on address bus is enabled. read rd output strobe signal indicating that external space is being read. high write hwr output strobe signal indicating that external space is to be written, and upper half (d 15 to d 8 ) of data bus is enabled. low write lwr output strobe signal indicating that external space is to be written, and lower half (d 7 to d 0 ) of data bus is enabled. chip select 0 to 7 cs0 to cs7 output strobe signal indicating that areas 0 to 7 are selected. wait wait input wait request signal when accessing external 3-state access space. bus request breq input request signal that releases bus to external device. bus request acknowledge back output acknowledge signal indicating that bus has been released. 6.1.4 register configuration table 6-2 summarizes the registers of the bus controller. table 6-2 bus controller registers initial value name abbreviation r/w power-on reset manual reset address * 1 bus width control register abwcr r/w h'ff/h'00 * 2 retained h'fed0 access state control register astcr r/w h'ff retained h'fed1 wait control register h wcrh r/w h'ff retained h'fed2 wait control register l wcrl r/w h'ff retained h'fed3 bus control register h bcrh r/w h'd0 retained h'fed4 bus control register l bcrl r/w h'3c retained h'fed5 notes: 1. lower 16 bits of the address. 2. determined by the mcu operating mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
126 6.2 register descriptions 6.2.1 bus width control register (abwcr) 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit : initial value : modes 1 to 3, 5 to 7 mode 4 : rw initial value : : rw abwcr is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. abwcr sets the data bus width for the external memory space. the bus width for on-chip memory and internal i/o registers is fixed regardless of the settings in abwcr. in normal mode, the settings of bits abw7 to abw1 have no effect on operation. after a power-on reset and in hardware standby mode, abwcr is initialized to h'ff in modes 1, 2, 3, and 5, 6, 7, and to h'00 in mode 4. it is not initialized by a manual reset or in software standby mode. bits 7 to 0area 7 to 0 bus width control (abw7 to abw0): these bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. in normal mode, only part of area 0 is enabled, and the abw0 bit selects whether external space is to be designated for 8-bit access or 16-bit access . bit n abwn description 0 area n is designated for 16-bit access 1 area n is designated for 8-bit access (n = 7 to 0) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
127 6.2.2 access state control register (astcr) 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value r/w : : : astcr is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. astcr sets the number of access states for the external memory space. the number of access states for on-chip memory and internal i/o registers is fixed regardless of the settings in astcr. in normal mode, the settings of bits ast7 to ast1 have no effect on operation. astcr is initialized to h'ff by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bits 7 to 0area 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. in normal mode, only part of area 0 is enabled, and the ast0 bit selects whether external space is to be designated for 2-state access or 3-state access. wait state insertion is enabled or disabled at the same time. bit n astn description 0 area n is designated for 2-state access wait state insertion in area n external space is disabled 1 area n is designated for 3-state access (initial value) wait state insertion in area n external space is enabled (n = 7 to 0) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
128 6.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable registers that select the number of program wait states for each area. in normal mode, only part of area is 0 is enabled, and bits w01 and w00 select the number of program wait states for the external space . the settings of bits w71, w70 to w11, and w10 have no effect on operation. program waits are not inserted in the case of on-chip memory or internal i/o registers. wcrh and wcrl are initialized to h'ff by a power-on reset and in hardware standby mode. they are not initialized by a manual reset or in software standby mode. (1) wcrh 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value r/w : : : bits 7 and 6area 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 bit 6 w71 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
129 bits 5 and 4area 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 bit 4 w61 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value) bits 3 and 2area 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 bit 2 w51 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value) bits 1 and 0area 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 bit 0 w41 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
130 (2) wcrl 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value r/w : : : bits 7 and 6area 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 bit 6 w31 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value) bits 5 and 4area 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 bit 4 w21 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
131 bits 3 and 2area 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 bit 2 w11 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value) bits 1 and 0area 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 bit 0 w01 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value) 6.2.4 bus control register h (bcrh) 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : bcrh is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. bcrh is initialized to h'd0 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
132 bit 7idle cycle insert 1 (icis1): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. bit 7 icis1 description 0 idle cycle not inserted in case of successive external read cycles in different areas 1 idle cycle inserted in case of successive external read cycles in different areas (initial value) bit 6idle cycle insert 0 (icis0): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . bit 6 icis0 description 0 idle cycle not inserted in case of successive external read and external write cycles 1 idle cycle inserted in case of successive external read and external write cycles (initial value) bit 5burst rom enable (brstrm): selects whether area 0 is used as a burst rom interface. in normal mode, the selection can be made from the entire external space . bit 5 brstrm description 0 area 0 is basic bus interface (initial value) 1 area 0 is burst rom interface bit 4burst cycle select 1 (brsts1): selects the number of burst cycles for the burst rom interface. bit 4 brsts1 description 0 burst cycle comprises 1 state 1 burst cycle comprises 2 states (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
133 bit 3burst cycle select 0 (brsts0): selects the number of words that can be accessed in a burst rom interface burst access. bit 3 brsts0 description 0 max. 4 words in burst access (initial value) 1 max. 8 words in burst access bits 2 to 0reserved: only 0 should be written to these bits. 6.2.5 bus control register l (bcrl) 7 brle 0 r/w 6 0 r/w 5 eae 1 r/w 4 1 r/w 3 1 r/w 0 waite 0 r/w 2 1 r/w 1 0 r/w bit initial value r/w : : : bcrl is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, and enabling or disabling of wait pin input. bcrl is initialized to h'3c by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7bus release enable (brle): enables or disables external bus release. bit 7 brle description 0 external bus release is disabled. breq and back can be used as i/o ports. (initial value) 1 external bus release is enabled. bit 6reserved: only 0 should be written to this bit. bit 5external address enable (eae): selects whether addresses h'010000 to h'01ffff are to be internal addresses or external addresses. this setting is invalid in normal mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
134 bit 5 eae description 0 addresses h'010000 to h'01ffff are in on-chip rom (in the h8s/2355) or a reserved area * (in the h8s/2353) 1 addresses h'010000 to h'01ffff are external addresses (external expansion mode) or a reserved area * (single-chip mode) (initial value) note: * reserved areas should not be accessed. bits 4 to 2reserved: only 1 should be written to these bits. bit 1reserved: only 0 should be written to this bit. bit 0wait pin enable (waite): selects enabling or disabling of wait input by the wait pin. bit 0 waite description 0 wait input by wait pin disabled. wait pin can be used as i/o port. (initial value) 1 wait input by wait pin enabled 6.3 overview of bus control 6.3.1 area partitioning in advanced mode, the bus controller partitions the 16 mbytes address space into eight areas, 0 to 7, in 2-mbyte units, and performs bus control for external space in area units. in normal mode, it controls a 64-kbyte address space comprising part of area 0. figure 6-2 shows an outline of the memory map. chip select signals ( cs0 to cs7 ) can be output for each area. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
135 area 0 (2mbytes) h'000000 h'ffffff (1) (2) h'0000 h'1fffff h'200000 area 1 (2mbytes) h'3fffff h'400000 area 2 (2mbytes) h'5fffff h'600000 area 3 (2mbytes) h'7fffff h'800000 area 4 (2mbytes) h'9fffff h'a00000 area 5 (2mbytes) h'bfffff h'c00000 area 6 (2mbytes) h'dfffff h'e00000 area 7 (2mbytes) h'ffff advanced mode normal mode figure 6-2 overview of area partitioning www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
136 6.3.2 bus specifications the external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller. (1) bus width: a bus width of 8 or 16 bits can be selected with adwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. when the burst rom interface is designated, 16-bit bus mode is always set. (2) number of access states: two or three access states can be selected with astcr. an area for which 2-state access is selected functions as a 2-state access space, and an area for which 3- state access is selected functions as a 3-state access space. with the burst rom interface, the number of access states may be determined without regard to astcr. when 2-state access space is designated, wait insertion is disabled. (3) number of program wait states: when 3-state access space is designated by astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. table 6-3 shows the bus specifications for each basic bus interface area. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
137 table 6-3 bus specifications for each area (basic bus interface) abwcr astcr wcrh, wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 0016 2 0 100 3 0 11 10 2 13 108 2 0 100 3 0 11 10 2 13 6.3.3 memory interfaces the h8s/2355 series memory interfaces comprise a basic bus interface that allows direct connection of rom, sram, and so on, and a burst rom interface (for area 0 only) that allows direct connection of burst rom. an area for which the basic bus interface is designated functions as normal space, and an area for which the burst rom interface is designated functions as burst rom space. 6.3.4 advanced mode the initial state of each area is basic bus interface, 3-state access space. the initial bus width is selected according to the operating mode. the bus specifications described here cover basic items only, and the sections on each memory interface (6.4 and 6.5) should be referred to for further details. area 0: area 0 includes on-chip rom, and in rom-disabled expansion mode, all of area 0 is external space. in rom-enabled expansion mode, the space excluding on-chip rom is external space. when area 0 external space is accessed, the cs0 signal can be output. either basic bus interface or burst rom interface can be selected for area 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
138 areas 1 to 6: in external expansion mode, all of areas 1 to 6 is external space. when area 1 to 6 external space is accessed, the cs1 to cs6 pin signals respectively can be output. only the basic bus interface can be used for areas 1 to 6. area 7: area 7 includes the on-chip ram and internal i/o registers. in external expansion mode, the space excluding the on-chip ram and internal i/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space. when area 7 external space is accessed, the cs7 signal can be output. only the basic bus interface can be used for the area 7 memory interface. 6.3.5 areas in normal mode in normal mode, a 64-kbyte address space comprising part of area 0 is controlled. area partitioning is not performed in normal mode. in rom-disabled expansion mode, the space excluding the on-chip ram and internal i/o registers is external space. in rom-enabled expansion mode the space excluding the on-chip rom, on-chip ram, and internal i/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space . when external space is accessed, the cs0 signal can be output. the basic bus interface or burst rom interface can be selected. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
139 6.3.6 chip select signals the h8s/2355 series can output chip select signals ( cs0 to cs7 ) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. in normal mode, only the cs0 signal can be output. figure 6-3 shows an example of csn (n = 0 to 7) output timing. enabling or disabling of the csn signal is performed by setting the data direction register (ddr) for the port corresponding to the particular csn pin. in rom-disabled expansion mode, the cs0 pin is placed in the output state after a power-on reset. pins cs1 to cs7 are placed in the input state after a power-on reset, and so the corresponding ddr should be set to 1 when outputting signals cs1 to cs7 . in rom-enabled expansion mode, pins cs0 to cs7 are all placed in the input state after a power- on reset, and so the corresponding ddr should be set to 1 when outputting signals cs0 to cs7 . for details, see section 8, i/o ports. bus cycle t 1 t 2 t 3 area n external address address bus csn figure 6-3 csn signal output timing (n = 0 to 7) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
140 6.4 basic bus interface 6.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl (see table 6-3). 6.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (d 15 to d 8 ) or lower data bus (d 7 to d 0 ) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-bit access space: figure 6-4 illustrates data alignment control for the 8-bit access space. with the 8-bit access space, the upper data bus (d 15 to d 8 ) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. d 15 d 8 d 7 d 0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 6-4 access sizes and data alignment control (8-bit access space) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
141 16-bit access space: figure 6-5 illustrates data alignment control for the 16-bit access space. with the 16-bit access space, the upper data bus (d 15 to d 8 ) and lower data bus (d 7 to d 0 ) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d 15 d 8 d 7 d 0 upper data bus byte size word size 1st bus cycle 2nd bus cycle longword size ?even address byte size ?odd address lower data bus figure 6-5 access sizes and data alignment control (16-bit access space) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
142 6.4.3 valid strobes table 6-4 shows the data buses used and valid strobes for the access spaces. in a read, the rd signal is valid without discrimination between the upper and lower halves of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half. table 6-4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d 15 to d 8 ) lower data bus (d 7 to d 0 ) 8-bit access byte read rd valid invalid space write hwr hi-z 16-bit access byte read even rd valid invalid space odd invalid valid write even hwr valid hi-z odd lwr hi-z valid word read rd valid valid write hwr , lwr valid valid note: hi-z: high impedance. invalid: input state; input value is ignored. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
143 6.4.4 basic timing 8-bit 2-state access space: figure 6-6 shows the bus timing for an 8-bit 2-state access space. when an 8-bit access space is accessed , the upper half (d 15 to d 8 ) of the data bus is used. the lwr pin is fixed high. wait states cannot be inserted. bus cycle t 1 t 2 address bus csn as rd d 15 to d 8 valid d 7 to d 0 invalid read hwr lwr d 15 to d 8 valid d 7 to d 0 write note: n = 0 to 7 high high impedance figure 6-6 bus timing for 8-bit 2-state access space www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
144 8-bit 3-state access space: figure 6-7 shows the bus timing for an 8-bit 3-state access space. when an 8-bit access space is accessed, the upper half (d 15 to d 8 ) of the data bus is used. the lwr pin is fixed high. wait states can be inserted. bus cycle t 1 t 2 address bus csn as rd d 15 to d 8 valid d 7 to d 0 invalid read hwr lwr d 15 to d 8 valid d 7 to d 0 high impedance write high note: n = 0 to 7 t 3 figure 6-7 bus timing for 8-bit 3-state access space www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
145 16-bit 2-state access space: figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. when a 16-bit access space is accessed, the upper half (d 15 to d 8 ) of the data bus is used for the even address, and the lower half (d 7 to d 0 ) for the odd address. wait states cannot be inserted. bus cycle t 1 t 2 address bus csn as rd d 15 to d 8 valid d 7 to d 0 invalid read hwr lwr d 15 to d 8 valid d 7 to d 0 write high note: n = 0 to 7 high impedance figure 6-8 bus timing for 16-bit 2-state access space (1) (even address byte access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
146 bus cycle t 1 t 2 address bus csn as rd d 15 to d 8 invalid d 7 to d 0 valid read hwr lwr d 15 to d 8 d 7 to d 0 valid write note: n = 0 to 7 high high impedance figure 6-9 bus timing for 16-bit 2-state access space (2) (odd address byte access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
147 bus cycle t 1 t 2 address bus csn as rd d 15 to d 8 valid d 7 to d 0 valid read hwr lwr d 15 to d 8 valid d 7 to d 0 valid write note: n = 0 to 7 figure 6-10 bus timing for 16-bit 2-state access space (3) (word access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
148 16-bit 3-state access space: figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. when a 16-bit access space is accessed , the upper half (d 15 to d 8 ) of the data bus is used for the even address, and the lower half (d 7 to d 0 ) for the odd address. wait states can be inserted. bus cycle t 1 t 2 address bus csn as rd d 15 to d 8 valid d 7 to d 0 invalid read hwr lwr d 15 to d 8 valid d 7 to d 0 high impedance write high note: n = 0 to 7 t 3 figure 6-11 bus timing for 16-bit 3-state access space (1) (even address byte access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
149 bus cycle t 1 t 2 address bus csn as rd d 15 to d 8 invalid d 7 to d 0 valid read hwr lwr d 15 to d 8 d 7 to d 0 valid write high note: n = 0 to 7 t 3 high impedance figure 6-12 bus timing for 16-bit 3-state access space (2) (odd address byte access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
150 bus cycle t 1 t 2 address bus csn as rd d 15 to d 8 valid d 7 to d 0 valid read hwr lwr d 15 to d 8 valid d 7 to d 0 valid write note: n = 0 to 7 t 3 figure 6-13 bus timing for 16-bit 3-state access space (3) (word access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
151 6.4.5 wait control when accessing external space, the h8s/2355 series can extend the bus cycle by inserting one or more wait states (t w ). there are two ways of inserting wait states: program wait insertion and pin wait insertion using the wait pin. program wait insertion from 0 to 3 wait states can be inserted automatically between the t 2 state and t 3 state on an individual area basis in 3-state access space, according to the settings of bwcrh and bwcrl. pin wait insertion setting the waite bit in bcrl to 1 enables wait insertion by means of the wait pin. program wait insertion is first carried out according to the settings in wcrh and wcrl. then , if the wait pin is low at the falling edge of ? in the last t 2 or t w state, a t w state is inserted. if the wait pin is held low, t w states are inserted until it goes high. this is useful when inserting four or more t w states, or when changing the number of t w states for different external devices. the waite bit setting applies to all areas. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
152 figure 6-14 shows an example of wait state insertion timing. by program wait t 1 address bus as rd data bus read data read hwr, lwr write data write note: indicates the timing of wait pin sampling. wait data bus t 2 t w t w t w t 3 by wait pin figure 6-14 example of wait state insertion timing the settings after a power-on reset are: 3-state access, 3 program wait state insertion, and wait input disabled. when a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
153 6.5 burst rom interface 6.5.1 overview with the h8s/2355 series, external space area 0 can be designated as burst rom space, and burst rom interfacing can be performed. the burst rom space interface enables 16-bit configuration rom with burst access capability to be accessed at high speed. area 0 can be designated as burst rom space by means of the brstrm bit in bcrh. consecutive burst accesses of a maximum of 4 words or 8 words can be performed for cpu instruction fetches only. one or two states can be selected for burst access. 6.5.2 basic timing the number of states in the initial cycle (full access) of the burst rom interface is in accordance with the setting of the ast0 bit in astcr. also, when the ast0 bit is set to 1, wait state insertion is possible. one or two states can be selected for the burst cycle, according to the setting of the brsts1 bit in bcrh. wait states cannot be inserted. when area 0 is designated as burst rom space, it becomes 16-bit access space regardless of the setting of the abw0 bit in abwcr. when the brsts0 bit in bcrh is cleared to 0, burst access of up to 4 words is performed; when the brsts0 bit is set to 1, burst access of up to 8 words is performed. the basic access timing for burst rom space is shown in figures 6-15 (a) and (b). the timing shown in figure 6-15 (a) is for the case where the ast0 and brsts1 bits are both set to 1, and that in figure 6-15 (b) is for the case where both these bits are cleared to 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
154 t 1 address bus cs0 as data bus t 2 t 3 t 1 t 2 t 1 full access t 2 rd burst access only lower address changed read data read data read data figure 6-15 (a) example of burst rom access timing (when ast0 = brsts1 = 1) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
155 t 1 address bus cs0 as data bus t 2 t 1 t 1 full access rd burst access only lower address changed read data read data read data figure 6-15 (b) example of burst rom access timing (when ast0 = brsts1 = 0) 6.5.3 wait control as with the basic bus interface, either program wait insertion or pin wait insertion using the wait pin can be used in the initial cycle (full access) of the burst rom interface. see section 6.4.5, wait control. wait states cannot be inserted in a burst cycle. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
156 6.6 idle cycle 6.6.1 operation when the h8s/2355 series accesses external space , it can insert a 1-state idle cycle (t i ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, with a long output floating time, and high-speed memory, i/o interfaces, and so on. (1) consecutive reads between different areas if consecutive reads between different areas occur while the icis1 bit in bcrh is set to 1, an idle cycle is inserted at the start of the second read cycle. this is enabled in advanced mode. figure 6-16 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a read cycle from sram, each being located in a different area. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b bus cycle a bus cycle b long output floating time data collision (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) t 1 address bus rd data bus t 2 t 3 t i t 1 t 2 cs (area a) cs (area b) cs (area a) cs (area b) figure 6-16 example of idle cycle operation (1) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
157 (2) write after read if an external write occurs after an external read while the icis0 bit in bcrh is set to 1, an idle cycle is inserted at the start of the write cycle. figure 6-17 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision t 1 address bus ? rd bus cycle a data bus t 2 t 3 t i t 1 bus cycle b t 2 hwr hwr cs (area a) cs (area b) cs (area a) cs (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 6-17 example of idle cycle operation (2) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
158 (3) relationship between chip select ( cs ) signal and read ( rd ) signal depending on the systems load conditions, the rd signal may lag behind the cs signal. an example is shown in figure 6.18. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle a rd signal and the bus cycle b cs signal. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset release, idle cycle insertion (b) is set. t 1 address bus rd bus cycle a t 2 t 3 t 1 t 2 bus cycle b possibility of overlap between cs (area b) and rd t 1 address bus bus cycle a t 2 t 3 t i t 1 bus cycle b t 2 cs (area a) cs (area b) rd cs (area a) cs (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 6.18 relationship between chip select ( cs ) and read ( rd ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
159 6.6.2 pin states in idle cycle table 6-5 shows pin states in an idle cycle. table 6-5 pin states in idle cycle pins pin state a 23 to a 0 contents of next bus cycle d 15 to d 0 high impedance csn high as high rd high hwr high lwr high www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
160 6.7 bus release 6.7.1 overview the h8s/2355 series can release the external bus in response to a bus request from an external device. in the external bus released state, the internal bus master continues to operate as long as there is no external access. 6.7.2 operation in external expansion mode, the bus can be released to an external device by setting the brle bit in bcrl to 1. driving the breq pin low issues an external bus request to the h8s/2355 series. when the breq pin is sampled, at the prescribed timing the back pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. in the external bus released state, an internal bus master can perform accesses using the internal bus. when an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. when the breq pin is driven high, the back pin is driven high at the prescribed timing and the external bus released state is terminated. in the event of simultaneous external bus release request and external access request generation, the order of priority is as follows: (high) external bus release > internal bus master external access (low) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
161 6.7.3 pin states in external bus released state table 6-6 shows pin states in the external bus released state. table 6-6 pin states in bus released state pins pin state a 23 to a 0 high impedance d 15 to d 0 high impedance csn high impedance as high impedance rd high impedance hwr high impedance lwr high impedance www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
162 6.7.4 transition timing figure 6-19 shows the timing for transition to the bus-released state. cpu cycle external bus released state cpu cycle address minimum 1 state t 0 t 1 t 2 address bus data bus as hwr , lwr breq back high impedance [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] low level of breq pin is sampled at rise of t 2 state. back pin is driven low at end of cpu read cycle, releasing bus to external bus master. breq pin state is still sampled in external bus released state. high level of breq pin is sampled. back pin is driven high, ending bus release cycle. high impedance high impedance high impedance rd high impedance figure 6-19 bus-released state transition timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
163 6.7.5 usage note when mstpcr is set to h'ffff or h'efff and a transition is made to sleep mode, the external bus release function halts. therefore, mstpcr should not be set to h'ffff or h'efff if the external bus release function is to be used in sleep mode. 6.8 bus arbitration 6.8.1 overview the h8s/2355 series has a bus arbiter that arbitrates bus master operations. there are two bus masters, the cpu and dtc, which perform read/write operations when they have possession of the bus. each bus master requests the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. the selected bus master then takes possession of the bus and begins its operation. 6.8.2 operation the bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dtc > cpu (low) an internal bus access by an internal bus master, and external bus release, can be executed in parallel. in the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (high) external bus release > internal bus master external access (low) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
164 6.8.3 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specific times at which each bus master can relinquish the bus. cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: the bus is transferred at a break between bus cycles. however, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. see appendix a-5, bus states during instruction execution, for timings at which the bus is not transferred. if the cpu is in sleep mode, it transfers the bus immediately. dtc: the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). it does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 6.8.4 external bus release usage note external bus release can be performed on completion of an external bus cycle. the rd signal and cs0 to cs7 signals remain low until the end of the external bus cycle. therefore, when external bus release is performed, the rd and cs0 to cs7 signals may change from the low level to the high-impedance state. 6.9 resets and the bus controller in a power-on reset, the h8s/2355, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. in a manual reset, the bus controllers registers and internal state are maintained, and an executing external bus cycle is completed. in this case, wait input is ignored and write data is not guaranteed. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
165 section 7 data transfer controller 7.1 overview the h8s/2355 series includes a data transfer controller (dtc). the dtc can be activated by an interrupt or software, to transfer data. 7.1.1 features the features of the dtc are: transfer possible over any number of channels ? transfer information is stored in memory ? one activation source can trigger a number of data transfers (chain transfer) wide range of transfer modes ? normal, repeat, and block transfer modes available ? incrementing, decrementing, and fixing of source and destination addresses can be selected direct specification of 16-mbyte address space possible ? 24-bit transfer source and destination addresses can be specified transfer can be set in byte or word units a cpu interrupt can be requested for the interrupt that activated the dtc ? an interrupt request can be issued to the cpu after one data transfer ends ? an interrupt request can be issued to the cpu after the specified data transfers have completely ended activation by software is possible module stop mode can be set ? the initial setting enables dtc registers to be accessed. dtc operation is halted by setting module stop mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
166 7.1.2 block diagram figure 7-1 shows a block diagram of the dtc. the dtcs register information is stored in the on-chip ram*. a 32-bit bus connects the dtc to the on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information and hence helping to increase processing speed. note: * when the dtc is used, the rame bit in syscr must be set to 1. interrupt request interrupt controller dtc internal address bus dtc service request control logic register information mra mrb cra crb dar sar cpu interrupt request on-chip ram internal data bus legend mra, mrb cra, crb sar dar dtcera to dtcerf dtvecr dtcera to dtcerf dtvecr : dtc mode registers a and b : dtc transfer count registers a and b : dtc source address register : dtc destination address register : dtc enable registers a to f : dtc vector register figure 7-1 block diagram of dtc www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
167 7.1.3 register configuration table 7-1 summarizes the dtc registers. table 7-1 dtc registers name abbreviation r/w initial value address * 1 dtc mode register a mra * 2 undefined * 3 dtc mode register b mrb * 2 undefined * 3 dtc source address register sar * 2 undefined * 3 dtc destination address register dar * 2 undefined * 3 dtc transfer count register a cra * 2 undefined * 3 dtc transfer count register b crb * 2 undefined * 3 dtc enable registers dtcer r/w h'00 h'ff30 to h'ff35 dtc vector register dtvecr r/w h'00 h'ff37 module stop control register mstpcr r/w h'3fff h'ff3c notes: 1. lower 16 bits of the address. 2. registers within the dtc cannot be read or written to directly. 3. register information is located in on-chip ram addresses h'f800 to h'fbff. it cannot be located in external space. when the dtc is used, do not clear the rame bit in syscr to 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
168 7.2 register descriptions 7.2.1 dtc mode register a (mra) mra is an 8-bit register that controls the dtc operating mode. 7 sm1 6 sm0 5 dm1 4 dm0 3 md1 0 sz 2 md0 1 dts bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined bits 7 and 6source address mode 1 and 0 (sm1, sm0): these bits specify whether sar is to be incremented, decremented, or left fixed after a data transfer. bit 7 bit 6 sm1 sm0 description 0 sar is fixed 1 0 sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 sar is decremented after a transfer (by C1 when sz = 0; by C2 when sz = 1) bits 5 and 4destination address mode 1 and 0 (dm1, dm0): these bits specify whether dar is to be incremented, decremented, or left fixed after a data transfer. bit 5 bit 4 dm1 dm0 description 0 dar is fixed 1 0 dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 dar is decremented after a transfer (by C1 when sz = 0; by C2 when sz = 1) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
169 bits 3 and 2dtc mode (md1, md0): these bits specify the dtc transfer mode. bit 3 bit 2 md1 md0 description 0 0 normal mode 1 repeat mode 1 0 block transfer mode 1 bit 1dtc transfer mode select (dts): specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. bit 1 dts description 0 destination side is repeat area or block area 1 source side is repeat area or block area bit 0dtc data transfer size (sz): specifies the size of data to be transferred. bit 0 sz description 0 byte-size transfer 1 word-size transfer www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
170 7.2.2 dtc mode register b (mrb) 7 chne 6 disel 5 4 3 0 2 1 bit initial value : : r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined mrb is an 8-bit register that controls the dtc operating mode. bit 7dtc chain transfer enable (chne): specifies chain transfer. with chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. in data transfer with chne set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of dtcer is not performed. bit 7 chne description 0 end of dtc data transfer (activation waiting state is entered) 1 dtc chain transfer (new register information is read, then data is transferred) bit 6dtc interrupt select (disel): specifies whether interrupt requests to the cpu are disabled or enabled after a data transfer. bit 6 disel description 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 (the dtc clears the interrupt source flag of the activating interrupt to 0) 1 after a data transfer ends, the cpu interrupt is enabled (the dtc does not clear the interrupt source flag of the activating interrupt to 0) bits 5 to 0reserved: these bits have no effect on dtc operation in the h8s/2355 series, and should always be written with 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
171 7.2.3 dtc source address register (sar) 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 7.2.4 dtc destination address register (dar) 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 7.2.5 dtc transfer count register a (cra) 15 14 13 12 11109876543210 crah cral bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined cra is a 16-bit register that designates the number of times data is to be transferred by the dtc. in normal mode, the entire cra functions as a 16-bit transfer counter (1 to 65536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. in repeat mode or block transfer mode, the cra is divided into two parts: the upper 8 bits (crah) and the lower 8 bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent when the count reaches h'00. this operation is repeated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
172 7.2.6 dtc transfer count register b (crb) 15 14 13 12 11109876543210 bit initial value : : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined r/w : crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. 7.2.7 dtc enable registers (dtcer) 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value r/w : : : the dtc enable registers comprise six 8-bit readable/writable registers, dtcera to dtcerf, with bits corresponding to the interrupt sources that can activate the dtc. these bits enable or disable dtc service for the corresponding interrupt sources. the dtc enable registers are initialized to h'00 by a reset and in hardware standby mode. bit ndtc activation enable (dtcen) bit n dtcen description 0 dtc activation by this interrupt is disabled (initial value) [clearing conditions] when the disel bit is 1 and the data transfer has ended when the specified number of transfers have ended 1 dtc activation by this interrupt is enabled [holding condition] when the disel bit is 0 and the specified number of transfers have not ended (n = 7 to 0) a dtce bit can be set for each interrupt source that can activate the dtc. the correspondence between interrupt sources and dtce bits is shown in table 7-4, together with the vector number generated for each interrupt controller. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
173 for dtce bit setting, use bit manipulation instructions such as bset and bclr. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 7.2.8 dtc vector register (dtvecr) 7 swdte 0 r/(w) * 6 dtvec6 0 r/w 5 dtvec5 0 r/w 4 dtvec4 0 r/w 3 dtvec3 0 r/w 0 dtvec0 0 r/w 2 dtvec2 0 r/w 1 dtvec1 0 r/w a value of 1 can always be written to the swdte bit, but 0 can only be written after 1 is read. bit initial value r/w : : : note: * dtvecr is an 8-bit readable/writable register that enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. dtvecr is initialized to h'00 by a reset and in hardware standby mode. bit 7dtc software activation enable (swdte): enables or disables dtc activation by software. when clearing the swdte bit to 0 by software, write 0 to swdte after reading swdte set to 1. bit 7 swdte description 0 dtc software activation is disabled (initial value) [clearing condition] when the disel bit is 0 and the specified number of transfers have not ended 1 dtc software activation is enabled [holding conditions] when the disel bit is 1 and data transfer has ended when the specified number of transfers have ended during data transfer due to software activation bits 6 to 0dtc software activation vectors 6 to 0 (dtvec6 to dtvec0): these bits specify a vector number for dtc software activation. the vector address is expressed as h'0400 + ((vector number) << 1). <<1 indicates a one-bit left- shift. for example, when dtvec6 to dtvec0 = h'10, the vector address is h'0420. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
174 7.2.9 module stop control register (mstpcr) 15 0 r/w bit initial value r/w : : : 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl mstpcr is a 16-bit readable/writable register that performs module stop mode control. when the mstp14 bit in mstpcr is set to 1, the dtc operation stops at the end of the bus cycle and a transition is made to module stop mode. however, 1 cannot be written in the mstp14 bit while the dtc is operating. for details, see section 19.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 14module stop (mstp14): specifies the dtc module stop mode. bit 14 mstp14 description 0 dtc module stop mode cleared (initial value) 1 dtc module stop mode set www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
175 7.3 operation 7.3.1 overview when activated, the dtc reads register information that is already stored in memory and transfers data on the basis of that register information. after the data transfer, it writes updated register information back to memory. pre-storage of register information in memory makes it possible to transfer data over any required number of channels. setting the chne bit to 1 makes it possible to perform a number of transfers with a single activation. figure 7-2 shows a flowchart of dtc operation. start read dtc vector next transfer read register information data transfer write register information clear an activation flag chne=1 end no no yes yes transfer counter= 0 or disel= 1 clear dtcer interrupt exception handling figure 7-2 flowchart of dtc operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
176 the dtc transfer mode can be normal mode, repeat mode, or block transfer mode. the 24-bit sar designates the dtc transfer source address and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed. table 7-2 outlines the functions of the dtc. table 7-2 dtc functions address registers transfer mode activation source transfer source transfer destination normal mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? up to 65,536 transfers possible repeat mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? after the specified number of transfers (1 to 256), the initial state resumes and operation continues block transfer mode ? one transfer request transfers a block of the specified size ? block size is from 1 to 256 bytes or words ? up to 65,536 transfers possible ? a block area can be designated at either the source or destination irq tpu tgi 8-bit timer cmi sci txi or rxi a/d converter adi software 24 bits 24 bits www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
177 7.3.2 activation sources the dtc operates when activated by an interrupt or by a write to dtvecr by software. an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dtcer bit. an interrupt becomes a dtc activation source when the corresponding bit is set to 1, and a cpu interrupt source when the bit is cleared to 0. at the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding dtcer bit is cleared. table 7-3 shows activation source and dtcer clearance. the activation source flag, in the case of rxi0, for example, is the rdrf flag of sci0. table 7-3 activation source and dtcer clearance activation source when the disel bit is 0 and the specified number of transfers have not ended when the disel bit is 1, or when the specified number of transfers have ended software activation the swdte bit is cleared to 0 the swdte bit remains set to 1 an interrupt is issued to the cpu interrupt activation the corresponding dtcer bit remains set to 1 the activation source flag is cleared to 0 the corresponding dtcer bit is cleared to 0 the activation source flag remains set to 1 a request is issued to the cpu for the activation source interrupt figure 7-3 shows a block diagram of activation source control. for details see section 5, interrupt controller. on-chip supporting module irq interrupt dtvecr selection circuit interrupt controller cpu dtc dtcer clear controller select interrupt request source flag cleared clear clear request interrupt mask figure 7-3 block diagram of dtc activation source control www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
178 when an interrupt has been designated a dtc activation source, existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities. 7.3.3 dtc vector table figure 7-4 shows the correspondence between dtc vector addresses and register information. table 7-4 shows the correspondence between activation, vector addresses, and dtcer bits. when the dtc is activated by software, the vector address is obtained from: h'0400 + (dtvecr[6:0] << 1) (where << 1 indicates a 1-bit left shift). for example, if dtvecr is h'10, the vector address is h'0420. the dtc reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. the register information can be placed at predetermined addresses in the on-chip ram. the start address of the register information should be an integral multiple of four. the configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. these two bytes specify the lower bits of the address in the on-chip ram. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
179 table 7-4 interrupt sources, dtc vector addresses, and corresponding dtces interrupt source origin of interrupt source vector number vector address dtce * priority write to dtvecr software dtvecr h'0400+ (dtvecr [6:0] <<1) high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 irq6 22 h'042c dtcea1 irq7 23 h'042e dtcea0 adi (a/d conversion end) a/d 28 h'0438 dtceb6 tgi0a (gr0a compare match/ input capture) tpu channel 0 32 h'0440 dtceb5 tgi0b (gr0b compare match/ input capture) 33 h'0442 dtceb4 tgi0c (gr0c compare match/ input capture) 34 h'0444 dtceb3 tgi0d (gr0d compare match/ input capture) 35 h'0446 dtceb2 tgi1a (gr1a compare match/ input capture) tpu channel 1 40 h'0450 dtceb1 tgi1b (gr1b compare match/ input capture) 41 h'0452 dtceb0 tgi2a (gr2a compare match/ input capture) tpu channel 2 44 h'0458 dtcec7 tgi2b (gr2b compare match/ input capture) 45 h'045a dtcec6 low www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
180 interrupt source origin of interrupt source vector number vector address dtce * priority tgi3a (gr3a compare match/ input capture) tpu channel 3 48 h'0460 dtcec5 high tgi3b (gr3b compare match/ input capture) 49 h'0462 dtcec4 tgi3c (gr3c compare match/ input capture) 50 h'0464 dtcec3 tgi3d (gr3d compare match/ input capture) 51 h'0466 dtcec2 tgi4a (gr4a compare match/ input capture) tpu channel 4 56 h'0470 dtcec1 tgi4b (gr4b compare match/ input capture) 57 h'0472 dtcec0 tgi5a (gr5a compare match/ input capture) tpu channel 5 60 h'0478 dtced5 tgi5b (gr5b compare match/ input capture) 61 h'047a dtced4 cmia0 8-bit timer 64 h'0480 dtced3 cmib0 channel 0 65 h'0482 dtced2 cmia1 8-bit timer 68 h'0488 dtced1 cmib1 channel 1 69 h'048a dtced0 rxi0 (reception complete 0) sci 81 h'04a2 dtcee3 txi0 (transmit data empty 0) channel 0 82 h'04a4 dtcee2 rxi1 (reception complete 1) sci 85 h'04aa dtcee1 txi1 (transmit data empty 1) channel 1 86 h'04ac dtcee0 rxi2 (reception complete 2) sci 89 h'04b2 dtcef7 txi2 (transmit data empty 2) channel 2 90 h'04b4 dtcef6 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
181 register information start address register information chain transfer dtc vector address figure 7-4 correspondence between dtc vector address and register information 7.3.4 location of register information in address space figure 7-5 shows how the register information should be located in the address space. locate the mra, sar, mrb, dar, cra, and crb registers, in that order, from the start address of the register information (contents of the vector address). in the case of chain transfer, register information should be located in consecutive areas. locate the register information in the on-chip ram (addresses: h'fff800 to h'fffbff). register information start address chain transfer register information for 2nd transfer in chain transfer mra sar mrb dar cra crb 4 bytes lower address cra crb register information mra 0 123 sar mrb dar figure 7-5 location of register information in address space www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
182 7.3.5 normal mode in normal mode, one operation transfers one byte or one word of data. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt can be requested. table 7-5 lists the register information in normal mode and figure 7-6 shows memory mapping in normal mode. table 7-5 register information in normal mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register a cra designates transfer count dtc transfer count register b crb not used transfer sar dar figure 7-6 memory mapping in normal mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
183 7.3.6 repeat mode in repeat mode, one operation transfers one byte or one word of data. from 1 to 256 transfers can be specified. once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. in repeat mode the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. table 7-6 lists the register information in repeat mode and figure 7-7 shows memory mapping in repeat mode. table 7-6 register information in repeat mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral designates transfer count (8 bits 2) dtc transfer count register b crb not used transfer sar or dar dar or sar repeat area figure 7-7 memory mapping in repeat mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
184 7.3.7 block transfer mode in block transfer mode, one operation transfers one block of data. the block size is 1 to 256. when the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. the other address register is then incremented, decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt is requested. table 7-7 lists the register information in block transfer mode and figure 7-8 shows memory mapping in block transfer mode. table 7-7 register information in block transfer mode name abbreviation function dtc source address register sar designates transfer source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral designates block size count dtc transfer count register b crb transfer count www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
185 transfer sar or dar dar or sar block area first block nth block figure 7-8 memory mapping in block transfer mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
186 7.3.8 chain transfer setting the chne bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 7-9 shows the memory map for chain transfer. source source destination destination dtc vector address register information start address register information chne = 1 register information chne = 0 figure 7-9 chain transfer memory map in the case of transfer with chne set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
187 7.3.9 operation timing figures 7-10 to 7-12 show an example of dtc operation timing. dtc activation request dtc request address vector read transfer information read transfer information write data transfer read write figure 7-10 dtc operation timing (example in normal mode or repeat mode) read write read write data transfer transfer information write transfer information read vector read dtc activation request dtc request address figure 7-11 dtc operation timing (example of block transfer mode, with block size of 2) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
188 read write read write address dtc activation request dtc request data transfer data transfer transfer information write transfer information write transfer information read transfer information read vector read figure 7-12 dtc operation timing (example of chain transfer) 7.3.10 number of dtc execution states table 7-8 lists execution statuses for a single dtc data transfer, and table 7-9 shows the number of states required for each execution status. table 7-8 dtc execution statuses mode vector read i register information read/write j data read k data write l internal operations m normal 1 6 1 1 3 repeat 1 6 1 1 3 block transfer 1 6 n n 3 n: block size (initial setting of crah and cral) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
189 table 7-9 number of states required for each execution status object to be accessed on- chip ram on- chip rom on-chip i/o registers external devices bus width 32 16 8 16 8 16 access states 11222323 vector read s i 1 4 6+2m 2 3+m execution status register s j information read/write byte data read s k word data read s k byte data write s l word data write s l 1 1 1 1 1 1 1 1 1 2 4 2 4 2 2 2 2 2 4 2 4 3+m 6+2m 3+m 6+2m 2 2 2 2 3+m 3+m 3+m 3+m internal operation s m 1 the number of execution states is calculated from the formula below. note that s means the sum of all transfers activated by one activation event (the number in which the chne bit is set to 1, plus 1). number of execution states = i s i + s (j s j + k s k + l s l ) + m s m for example, when the dtc vector address table is located in on-chip rom, normal mode is set, and data is transferred from the on-chip rom to an internal i/o register, the time required for the dtc operation is 13 states. the time from activation to the end of the data write is 10 states. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
190 7.3.11 procedures for using dtc activation by interrupt: the procedure for using the dtc with interrupt activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. [5] after the end of one data transfer, or after the specified number of data transfers have ended, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. activation by software: the procedure for using the dtc with software activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] check that the swdte bit is 0. [4] write 1 to swdte bit and the vector number to dtvecr. [5] check the vector number written to dtvecr. [6] after the end of one data transfer, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the specified number of data transfers have ended, the swdte bit is held at 1 and a cpu interrupt is requested. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
191 7.3.12 examples of use of the dtc (1) normal mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. [1] set mra to fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci rdr address in sar, the start address of the ram area where the data will be received in dar, and 128 (h'0080) in cra. crb can be set to any value. [2] set the start address of the register information at the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable the reception complete (rxi) interrupt. since the generation of a receive error during the sci reception operation will disable subsequent reception, the cpu should be enabled to accept receive error interrupts. [5] each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automatically cleared to 0. [6] when cra becomes 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine should perform wrap-up processing. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
192 (2) software activation an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. [1] set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. [2] set the start address of the register information at the dtc vector address (h'04c0). [3] check that the swdte bit in dtvecr is 0. check that there is currently no transfer activated by software. [4] write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. [5] read dtvecr again and check that it is set to the vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer, go back to step 3. [6] if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. [7] after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform other wrap-up processing. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
193 7.4 interrupts an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and interrupt controller priority level control. in the case of activation by software, a software activated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine should clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. 7.5 usage notes module stop: when the mstp14 bit in mstpcr is set to 1, the dtc clock stops, and the dtc enters the module stop state. however, 1 cannot be written in the mstp14 bit while the dtc is operating. on-chip ram: the mra, mrb, sar, dar, cra, and crb registers are all located in on-chip ram. when the dtc is used, the rame bit in syscr must not be cleared to 0. dtce bit setting: for dtce bit setting, use bit manipulation instructions such as bset and bclr. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
195 section 8 i/o ports 8.1 overview the h8s/2355 series has 12 i/o ports (ports 1, 2, 3, 5, 6, and a to g), and one input-only port (port 4). table 8-1 summarizes the port functions. the pins of each port also have other functions. each port includes a data direction register (ddr) that controls input/output (not provided for the input-only port), a data register (dr) that stores output data, and a port register (port) used to read the pin states. ports a to e have a built-in mos input pull-up function, and in addition to dr and ddr, have a mos input pull-up control register (pcr) to control the on/off state of mos input pull-up. ports 3 and a include an open-drain control register (odr) that controls the on/off state of the output buffer pmos. ports a to e can drive a single ttl load and 90 pf capacitive load, and ports 1, 2, 3, 5, 6, f, and g can drive a single ttl load and 30 pf capacitive load. all the i/o ports can drive a darlington transistor when in output mode. ports 1, and a to c can drive an led (10 ma sink current). port 2, and ports 6 4 to 6 7 and a 4 to a 7 , are schmitt-triggered inputs. for block diagrams of the ports see appendix c, i/o port block diagrams. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
196 table 8-1 port functions port description pins mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port 1 ? 8-bit i/o port p1 7 /tiocb2/ tclkd p1 6 /tioca2 p1 5 /tiocb1/ tclkc p1 4 /tioca1 p1 3 /tiocd0/ tclkb p1 2 /tiocc0/ tclka p1 1 /tiocb0 p1 0 /tioca0 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2) port 2 ? 8-bit i/o port ? schmitt- triggered input p2 7 /tiocb5/ tmo1 p2 6 /tioca5/ tmo0 p2 5 /tiocb4/ tmci1 p2 4 /tioca4/ tmri1 p2 3 /tiocd3/ tmci0 p2 2 /tiocc3/ tmri0 p2 1 /tiocb3 p2 0 /tioca3 8-bit i/o port also functioning as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, tiocb5), and 8-bit timer (channels 0 and 1) i/o pins (tmri0, tmci0, tmo0, tmri1, tmci1, tmo1) port 3 ? 6-bit i/o port ? open-drain output capability p3 5 /sck1 p3 4 /sck0 p3 3 /rxd1 p3 2 /rxd0 p3 1 /txd1 p3 0 /txd0 6-bit i/o port also functioning as sci (channels 0 and 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1) port 4 ? 8-bit input port p4 7 /an7/ da1 * 1 p4 6 /an6/ da0 * 1 p4 5 /an5 p4 4 /an4 p4 3 /an3 p4 2 /an2 p4 1 /an1 p4 0 /an0 8-bit input port also functioning as a/d converter analog inputs (an7 to an0) and d/a converter analog outputs (da1 and da0) * 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
197 port description pins mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port 5 ? 4-bit i/o port p5 3 / adtrg p5 2 /sck2 p5 1 /rxd2 p5 0 /txd2 4-bit i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2) and a/d converter input pin ( adtrg ) port 6 ? 8-bit i/o port ? schmitt- triggered input (p6 4 to p6 7 ) p6 7 / irq3 / cs7 p6 6 / irq2 / cs6 p6 5 / irq1 p6 4 / irq0 p6 3 p6 2 p6 1 / cs5 p6 0 / cs4 8-bit i/o port also functioning as interrupt input pins ( irq0 to irq3 ) 8-bit i/o port also functioning as bus control output pins ( cs4 to cs7 ), and interrupt input pins ( irq0 to irq3 ) 8-bit i/o port also function- ing as interrupt input pins ( irq0 to irq3 ) port a ? 8-bit i/o port ? built-in mos input pull-up ? open-drain output capability ? schmitt- triggered input (pa 4 to pa 7 ) pa 7 /a 23 / irq7 pa 6 /a 22 / irq6 pa 5 /a 21 / irq5 dual function as i/o ports and interrupt input pins ( irq7 to irq4 ) when ddr = 0 (after reset): dual function as input ports and interrupt input pins ( irq7 to irq5 ) when ddr = 1: address output when ddr = 0 (after reset): dual function as input ports and interrupt input pins ( irq7 to irq4 ) dual function as i/o ports and interrupt input pins ( irq7 to irq4 ) pa 4 /a 20 / irq4 address output when ddr = 1: address output pa 3 /a 19 to pa 0 /a 16 i/o ports address output when ddr = 0 (after reset): input ports when ddr = 1: address output i/o ports www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
198 port description pins mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port b ? 8-bit i/o port ? built-in mos input pull-up pb 7 /a 15 to pb 0 /a 8 address output when ddr = 0 (after reset): input port when ddr = 1: address output i/o port address output when ddr = 0 (after reset): input port when ddr = 1: address output i/o port port c ? 8-bit i/o port ? built-in mos input pull-up pc 7 /a 7 to pc 0 /a 0 address output when ddr = 0 (after reset): input port when ddr = 1: address output i/o port address output when ddr = 0 (after reset): input port when ddr = 1: address output i/o port port d ? 8-bit i/o port ? built-in mos input pull-up pd 7 /d 15 to pd 0 /d 8 data bus input/ output i/o port data bus input/output i/o port port e ? 8-bit i/o port ? built-in mos input pull-up pe 7 /d 7 to pe 0 /d 0 in 8-bit bus mode: i/o port in 16-bit bus mode: data bus input/output i/o port in 8-bit bus mode: i/o port in 16-bit bus mode: data bus input/output i/o port port f ? 8-bit i/o port pf 7 /? when ddr = 0: input port when ddr = 1 (after reset): ? output when ddr = 0 (after reset): input port when ddr = 1: ? output when ddr = 0: input port when ddr = 1 (after reset): ? output when ddr = 0 (after reset): input port when ddr = 1: ? output pf 6 / as pf 5 / rd pf 4 / hwr pf 3 / lwr as , rd , hwr , lwr output i/o port as , rd , hwr , lwr output i/o port www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
199 port description pins mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 port f ? 8-bit i/o port pf 2 / wait when waite = 0 (after reset): i/o port when waite = 1: wait input i/o port when waite = 0 (after reset): i/o port when waite = 1: wait input i/o port pf 1 / back pf 0 / breq when brle = 0 (after reset): i/o port when brle = 1: breq input, back output when brle = 0 (after reset): i/o port when brle = 1: breq input, back output port g ? 5-bit i/o port pg 4 / cs0 when ddr= 0 * 2 : input port when ddr= 1 * 3 : cs0 output i/o port when ddr = 0 * 2 : input port when ddr = 1 * 3 : cs0 output i/o port pg 3 / cs1 pg 2 / cs2 pg 1 / cs3 i/o port when ddr = 0 (after reset): input port when ddr = 1: cs1 , cs2 , cs3 output pg 0 i/o port notes: 1. as the h8s/2393 does not support a d/a converter, it does not have the da0 and da1 outputs. 2. after a reset in mode 2 or 6 3. after a reset in mode 1, 4 or 5 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
200 8.2 port 1 8.2.1 overview port 1 is an 8-bit i/o port. port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2). port 1 pin functions are the same in all operating modes. figure 8-1 shows the port 1 pin configuration. p1 7 (i/o)/tiocb2 (i/o)/tclkd (input) p1 6 (i/o)/tioca2 (i/o) p1 5 (i/o)/tiocb1 (i/o)/tclkc (input) p1 4 (i/o)/tioca1 (i/o) p1 3 (i/o)/tiocd0 (i/o)/tclkb (input) p1 2 (i/o)/tiocc0 (i/o)/tclka (input) p1 1 (i/o)/tiocb0 (i/o) p1 0 (i/o)/tioca0 (i/o) port 1 port 1 pins figure 8-1 port 1 pin functions 8.2.2 register configuration table 8-2 shows the port 1 register configuration. table 8-2 port 1 registers name abbreviation r/w initial value address * port 1 data direction register p1ddr w h'00 h'feb0 port 1 data register p1dr r/w h'00 h'ff60 port 1 register port1 r undefined h'ff50 note: * lower 16 bits of the address. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
201 port 1 data direction register (p1ddr) 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value r/w : : : p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. setting a p1ddr bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p1ddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. as the tpu is initialized by a manual reset, the pin states are determined by the p1ddr and p1dr specifications. port 1 data register (p1dr) 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit initial value r/w : : : p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p1 7 to p1 0 ). p1dr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port 1 register (port1) 7 p17 * r 6 p16 * r 5 p15 * r 4 p14 * r 3 p13 * r 0 p10 * r 2 p12 * r 1 p11 * r bit initial value r/w note: * determined by state of pins p1 7 to p1 0 . : : : port1 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 1 pins (p1 7 to p1 0 ) must always be performed on p1dr. if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
202 after a power-on reset and in hardware standby mode, port1 contents are determined by the pin states, as p1ddr and p1dr are initialized. port1 retains its prior state after a manual reset, and in software standby mode. 8.2.3 pin functions port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2). port 1 pin functions are shown in table 8-3. table 8-3 port 1 pin functions pin selection method and pin functions p1 7 /tiocb2/ tclkd the pin function is switched as shown below according to the combination of the tpu channel 2 setting by bits md3 to md0 in tmdr2, bits iob3 to iob0 in tior2, bits cclr1 and cclr0 in tcr2, bits tpsc2 to tpsc0 in tcr0 and tcr5, and bit p17ddr. tpu channel 2 setting table below (1) table below (2) p17ddr 0 1 pin function tiocb2 output p1 7 input p1 7 output tiocb2 input * 1 tclkd input * 2 notes: 1. tiocb2 input when md3 to md0 = b'0000, b'01xx, and iob3 = 1. 2. tclkd input when the setting for either tcr0 or tcr5 is: tpsc2 to tpsc0 = b'111. tclkd input when channels 2 and 4 are set to phase counting mode. tpu channel 2 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
203 pin selection method and pin functions p1 6 /tioca2 the pin function is switched as shown below according to the combination of the tpu channel 2 setting by bits md3 to md0 in tmdr2, bits ioa3 to ioa0 in tior2, bits cclr1 and cclr0 in tcr2, and bit p16ddr. tpu channel 2 setting table below (1) table below (2) p16ddr 0 1 pin function tioca2 output p1 6 input p1 6 output tioca2 input * 1 note: 1. tioca2 input when md3 to md0 = b'0000, b'01xx, and ioa3 = 1. tpu channel 2 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0011 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: dont care note: 2. tiocb2 output is disabled. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
204 pin selection method and pin functions p1 5 /tiocb1/ tclkc the pin function is switched as shown below according to the combination of the tpu channel 1 setting by bits md3 to md0 in tmdr1, bits iob3 to iob0 in tior1, bits cclr1 and cclr0 in tcr1, bits tpsc2 to tpsc0 in tcr0, tcr2, tcr4, and tcr5, and bit p15ddr. tpu channel 1 setting table below (1) table below (2) p15ddr 0 1 pin function tiocb1 output p1 5 input p1 5 output tiocb1 input * 1 tclkc input * 2 notes: 1. tiocb1 input when md3 to md0 = b'0000, b'01xx and iob3 to iob0 = b'10xx. 2. tclkc input when the setting for either tcr0 or tcr2 is: tpsc2 to tpsc0 = b'110; or when the setting for either tcr4 or tcr5 is tpsc2 to tpsc0 = b'101. tclkc input when channels 2 and 4 are set to phase counting mode. tpu channel 1 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
205 pin selection method and pin functions p1 4 /tioca1 the pin function is switched as shown below according to the combination of the tpu channel 1 setting by bits md3 to md0 in tmdr1, bits ioa3 to ioa0 in tior1, bits cclr1 and cclr0 in tcr1, and bit p14ddr. tpu channel 1 setting table below (1) table below (2) p14ddr 0 1 pin function tioca1 output p1 4 input p1 4 output tioca1 input * 1 note: 1. tioca1 input when md3 to md0 = b'0000, b'01xx, ioa3 to ioa0 = b'10xx. tpu channel 1 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: don't care note: 2. tiocb1 output is disabled. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
206 pin selection method and pin functions p1 3 /tiocd0/ tclkb the pin function is switched as shown below according to the combination of the tpu channel 0 setting by bits md3 to md0 in tmdr0, bits iod3 to iod0 in tior0l, bits cclr2 to cclr0 in tcr0, bits tpsc2 to tpsc0 in tcr0 to tcr2, and bit p13ddr. tpu channel 0 setting table below (1) table below (2) p13ddr 0 1 pin function tiocd0 output p1 3 input p1 3 output tiocd0 input * 1 tclkb input * 2 notes: 1. tiocd0 input when md3 to md0 = b'0000, iod3 to iod0 =b'10xx. 2. tclkb input when the setting for tcr0 to tcr2 is: tpsc2 to tpsc0 = b'101; tclkb input when channels 1 and 5 are set to phase counting mode. tpu channel 0 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'110 b'110 output function output compare output pwm mode 2 output x: dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
207 pin selection method and pin functions p1 2 /tiocc0/ tclka the pin function is switched as shown below according to the combination of the tpu channel 0 setting by bits md3 to md0 in tmdr0, bits ioc3 to ioc0 in tior0l, bits cclr2 to cclr0 in tcr0, bits tpsc2 to tpsc0 in tcr0 to tcr5, and bit p12ddr. tpu channel 0 setting table below (1) table below (2) p12ddr 0 1 pin function tiocc0 output p1 2 input p1 2 output tiocc0 input * 1 tclka input * 2 notes: 1. tiocc0 input when md3 to md0 = b'0000, and ioc3 to ioc0 = b'10xx. 2. tclka input when the setting for tcr0 to tcr5 is: tpsc2 to tpsc0 = b'100; tclka input when channels 1 and 5 are set to phase counting mode. tpu channel 0 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'101 b'101 output function output compare output pwm mode 1 output * 3 pwm mode 2 output x: dont care note: 3. tiocd0 output is disabled. when bfa = 1 or bfb = 1 in tmdr0, output is disabled and setting (2) applies. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
208 pin selection method and pin functions p1 1 /tiocb0 the pin function is switched as shown below according to the combination of the tpu channel 0 setting by bits md3 to md0 in tmdr0, bits iob3 to iob0 in tior0h, bits cclr2 to cclr0 in tcr0, and bit p11ddr. tpu channel 0 setting table below (1) table below (2) p11ddr 0 1 pin function tiocb0 output p1 1 input p1 1 output tiocb0 input * 1 note: 1. tiocb0 input when md3 to md0 = b'0000, and iob3 to iob0 = b'10xx. tpu channel 0 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'010 b'010 output function output compare output pwm mode 2 output x: dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
209 pin selection method and pin functions p1 0 /tioca0 the pin function is switched as shown below according to the combination of the tpu channel 0 setting by bits md3 to md0 in tmdr0, bits ioa3 to ioa0 in tior0h, bits cclr2 to cclr0 in tcr0, and bit p10ddr. tpu channel 0 setting table below (1) table below (2) p10ddr 0 1 pin function tioca0 output p1 0 input p1 0 output tioca0 input * 1 note: 1. tioca0 input when md3 to md0 = b'0000, and ioa3 to ioa0 = b'10xx. tpu channel 0 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'001 b'001 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: dont care note: 2. tiocb0 output is disabled. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
210 8.3 port 2 8.3.1 overview port 2 is an 8-bit i/o port. port 2 pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5), and 8-bit timer i/o pins (tmri0, tmci0, tmo0, tmri1, tmci1, and tmo1). port 2 pin functions are the same in all operating modes. port 2 uses schmitt-triggered input. figure 8-2 shows the port 2 pin configuration. p2 7 (i/o)/tiocb5 (i/o)/tmo1 (output) p2 6 (i/o)/tioca5 (i/o)/tmo0 (output) p2 5 (i/o)/tiocb4 (i/o)/tmci1 (input) p2 4 (i/o)/tioca4 (i/o)/tmri1 (input) p2 3 (i/o)/tiocd3 (i/o)/tmci0 (input) p2 2 (i/o)/tiocc3 (i/o)/tmri0 (input) p2 1 (i/o)/tiocb3 (i/o) p2 0 (i/o)/tioca3 (i/o) port 2 port 2 pins figure 8-2 port 2 pin functions 8.3.2 register configuration table 8-4 shows the port 2 register configuration. table 8-4 port 2 registers name abbreviation r/w initial value address* port 2 data direction register p2ddr w h'00 h'feb1 port 2 data register p2dr r/w h'00 h'ff61 port 2 register port2 r undefined h'ff51 note: * lower 16 bits of the address. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
211 port 2 data direction register (p2ddr) 7 p27ddr 0 w 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 0 p20ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w bit initial value r/w : : : p2ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. p2ddr cannot be read; if it is, an undefined value will be read. setting a p2ddr bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p2ddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. as the tpu and 8-bit timer are initialized by a manual reset, the pin states are determined by the p2ddr and p2dr specifications. port 2 data register (p2dr) 7 p27dr 0 r/w 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 0 p20dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w bit initial value r/w : : : p2dr is an 8-bit readable/writable register that stores output data for the port 2 pins (p2 7 to p2 0 ). p2dr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port 2 register (port2) 7 p27 * r 6 p26 * r 5 p25 * r 4 p24 * r 3 p23 * r 0 p20 * r 2 p22 * r 1 p21 * r bit initial value r/w : : : note: * determined by state of pins p2 7 to p2 0 . port2 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 2 pins (p2 7 to p2 0 ) must always be performed on p2dr. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
212 if a port 2 read is performed while p2ddr bits are set to 1, the p2dr values are read. if a port 2 read is performed while p2ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port2 contents are determined by the pin states, as p2ddr and p2dr are initialized. port2 retains its prior state after a manual reset, and in software standby mode. 8.3.3 pin functions port 2 pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5), and 8-bit timer i/o pins (tmri0, tmci0, tmo0, tmri1, tmci1, and tmo1). port 2 pin functions are shown in table 8-5. table 8-5 port 2 pin functions pin selection method and pin functions p2 7 /tiocb5/ tmo1 the pin function is switched as shown below according to the combination of the tpu channel 5 setting by bits md3 to md0 in tmdr5, bits iob3 to iob0 in tior5, bits cclr1 and cclr0 in tcr5, bits os3 to os0 in tcsr1, and bit p27ddr. os3 to os0 all 0 any 1 tpu channel 5 setting table below (1) table below (2) p27ddr 0 1 pin function tiocb5 output p2 7 input p2 7 output tmo1 output tiocb5 input * note: * tiocb5 input when md3 to md0 = b'0000, b'01xx, and iob3 = 1. tpu channel 5 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
213 pin selection method and pin functions p2 6 /tioca5/ tmo0 the pin function is switched as shown below according to the combination of the tpu channel 5 setting by bits md3 to md0 in tmdr5, bits ioa3 to ioa0 in tior5, bits cclr1 and cclr0 in tcr5, bits os3 to os0 in tcsr0, and bit p26ddr. os3 to os0 all 0 any 1 tpu channel 5 setting table below (1) table below (2) p26ddr 0 1 nder6 0 pin function tioca5 output p2 6 input p2 6 output tmo0 output tioca5 input * 1 note: 1. tioca5 input when md3 to md0 = b'0000, b'01xx, and ioa3 = 1. tpu channel 5 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: dont care note: 2. tiocb5 output is disabled. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
214 pin selection method and pin functions p2 5 /tiocb4/ tmci1 this pin is used as the 8-bit timer external clock input pin when external clock is selected with bits cks2 to cks0 in tcr1. the pin function is switched as shown below according to the combination of the tpu channel 4 setting by bits md3 to md0 in tmdr4 and bits iob3 to iob0 in tior4, bits cclr1 and cclr0 in tcr4, and bit p25ddr. tpu channel 4 setting table below (1) table below (2) p25ddr 0 1 pin function tiocb4 output p2 5 input p2 5 output tiocb4 input * 1 tmci1 input note: 1. tiocb4 input when md3 to md0 = b'0000, b'01xx, and iob3 to iob0 = b'10xx. tpu channel 4 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
215 pin selection method and pin functions p2 4 /tioca4/ tmri1 this pin is used as the 8-bit timer counter reset pin when bits cclr1 and cclr0 in tcr1 are both set to 1. the pin function is switched as shown below according to the combination of the tpu channel 4 setting by bits md3 to md0 in tmdr4, bits ioa3 to ioa0 in tior4, bits cclr1 and cclr0 in tcr4, and bit p24ddr. tpu channel 4 setting table below (1) table below (2) p24ddr 0 1 pin function tioca4 output p2 4 input p2 4 output tioca4 input * 1 tmri1 input note: 1. tioca4 input when md3 to md0 = b'0000, b'01xx, and ioa3 to ioa0 = b'10xx. tpu channel 4 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: dont care note: 2. tiocb4 output is disabled. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
216 pin selection method and pin functions p2 3 /tiocd3/ tmci0 this pin is used as the 8-bit timer external clock input pin when external clock is selected with bits cks2 to cks0 in tcr0. the pin function is switched as shown below according to the combination of the tpu channel 3 setting by bits md3 to md0 in tmdr3, bits iod3 to iod0 in tior3l, bits cclr2 to cclr0 in tcr3, and bit p23ddr. tpu channel 3 setting table below (1) table below (2) p23ddr 0 1 pin function tiocd3 output p2 3 input p2 3 output tiocd3 input * 1 tmci0 input note: 1. tiocd3 input when md3 to md0 = b'0000, and iod3 to iod0 = b'10xx. tpu channel 3 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'110 b'110 output function output compare output pwm mode 2 output x: dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
217 pin selection method and pin functions p2 2 /tiocc3/ tmci0 this pin is used as the 8-bit timer counter reset pin when bits cclr1 and cclr0 in tcr0 are both set to 1. the pin function is switched as shown below according to the combination of the tpu channel 3 setting by bits md3 to md0 in tmdr3, bits ioc3 to ioc0 in tior3l, bits cclr2 to cclr0 in tcr3, and bit p22ddr. tpu channel 3 setting table below (1) table below (2) p22ddr 0 1 pin function tiocc3 output p2 2 input p2 2 output tiocc3 input * 1 tmri0 input note: 1. tiocc3 input when md3 to md0 = b'0000, and ioc3 to ioc0 = b'10xx. tpu channel 3 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'101 b'101 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: dont care note: 2. tiocd3 output is disabled. when bfa = 1 or bfb = 1 in tmdr3, output is disabled and setting (2) applies. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
218 pin selection method and pin functions p2 1 /tiocb3 the pin function is switched as shown below according to the combination of the tpu channel 3 setting by bits md3 to md0 in tmdr3, bits iob3 to iob0 in tior3h, bits cclr2 to cclr0 in tcr3, and bit p21ddr. tpu channel 3 setting table below (1) table below (2) p21ddr 0 1 pin function tiocb3 output p2 1 input p2 1 output tiocb3 input * 1 note: 1. tiocb3 input when md3 to md0 = b'0000, and iob3 to iob0 = b'10xx. tpu channel 3 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'010 b'010 output function output compare output pwm mode 2 output x: dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
219 pin selection method and pin functions p2 0 /tioca3 the pin function is switched as shown below according to the combination of the tpu channel 3 setting by bits md3 to md0 in tmdr3, bits ioa3 to ioa0 in tior3h, bits cclr2 to cclr0 in tcr3, and bit p20ddr. tpu channel 3 setting table below (1) table below (2) p20ddr 0 1 pin function tioca3 output p2 0 input p2 0 output tioca3 input * 1 note: 1. tioca3 input when md3 to md0 = b'0000, and ioa3 to ioa0 = b'10xx. tpu channel 3 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'001 b'001 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: dont care note: 2. tiocb3 output is disabled. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
220 8.4 port 3 8.4.1 overview port 3 is a 6-bit i/o port. port 3 pins also function as sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, and sck1). port 3 pin functions are the same in all operating modes. figure 8-3 shows the port 3 pin configuration. p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ sck1 (i/o) sck0 (i/o) rxd1 (input) rxd0 (input) txd1 (output) txd0 (output) port 3 pins port 3 figure 8-3 port 3 pin functions 8.4.2 register configuration table 8-6 shows the port 3 register configuration. table 8-6 port 3 registers name abbreviation r/w initial value * 2 address * 1 port 3 data direction register p3ddr w h'00 h'feb2 port 3 data register p3dr r/w h'00 h'ff62 port 3 register port3 r undefined h'ff52 port 3 open drain control register p3odr r/w h'00 h'ff76 notes: 1. lower 16 bits of the address. 2. value of bits 5 to 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
221 port 3 data direction register (p3ddr) 7 undefined 6 undefined 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w bit initial value r/w : : : p3ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. bits 7 and 6 are reserved. p3ddr cannot be read; if it is, an undefined value will be read. setting a p3ddr bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p3ddr is initialized to h'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. as the sci is initialized, the pin states are determined by the p3ddr and p3dr specifications. port 3 data register (p3dr) 7 undefined 6 undefined 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit initial value r/w : : : p3dr is an 8-bit readable/writable register that stores output data for the port 3 pins (p3 5 to p3 0 ). bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. p3dr is initialized to h'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
222 port 3 register (port3) 7 undefined 6 undefined 5 p35 * r 4 p34 * r 3 p33 * r 0 p30 * r 2 p32 * r 1 p31 * r bit initial value r/w : : : note: * determined by state of pins p3 5 to p3 0 . port3 is an 8-bit read-only register that shows the pin states. writing of output data for the port 3 pins (p3 5 to p3 0 ) must always be performed on p3dr. bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port3 contents are determined by the pin states, as p3ddr and p3dr are initialized. port3 retains its prior state after a manual reset, and in software standby mode. port 3 open drain control register (p3odr) 7 undefined 6 undefined 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w bit initial value r/w : : : p3odr is an 8-bit readable/writable register that controls the pmos on/off status for each port 3 pin (p3 5 to p3 0 ). bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. setting a p3odr bit to 1 makes the corresponding port 3 pin an nmos open-drain output pin, while clearing the bit to 0 makes the pin a cmos output pin. p3odr is initialized to h'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
223 8.4.3 pin functions port 3 pins also function as sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, and sck1). port 3 pin functions are shown in table 8-7. table 8-7 port 3 pin functions pin selection method and pin functions p3 5 /sck1 the pin function is switched as shown below according to the combination of bit c/ a in the sci1 smr, bits cke0 and cke1 in scr, and bit p35ddr. cke1 0 1 c/ a 01 cke0 0 1 p35ddr 0 1 pin function p3 5 input pin p3 5 output pin * sck1 output pin * sck1 output pin * sck1 input pin note: * when p35odr = 1, the pin becomes an nmos open-drain output. p3 4 /sck0 the pin function is switched as shown below according to the combination of bit c/ a in the sci0 smr, bits cke0 and cke1 in scr, and bit p34ddr. cke1 0 1 c/ a 01 cke0 0 1 p34ddr 0 1 pin function p3 4 input pin p3 4 output pin * sck0 output pin * sck0 output pin * sck0 input pin note: * when p34odr = 1, the pin becomes an nmos open-drain output. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
224 pin selection method and pin functions p3 3 /rxd1 the pin function is switched as shown below according to the combination of bit re in the sci1 scr, and bit p33ddr. re 0 1 p33ddr 0 1 pin function p3 3 input pin p3 3 output pin * rxd1 input pin note: * when p33odr = 1, the pin becomes an nmos open-drain output. p3 2 /rxd0 the pin function is switched as shown below according to the combination of bit re in the sci0 scr, and bit p32ddr. re 0 1 p32ddr 0 1 pin function p3 2 input pin p3 2 output pin * rxd0 input pin note: * when p32odr = 1, the pin becomes an nmos open-drain output. p3 1 /txd1 the pin function is switched as shown below according to the combination of bit te in the sci1 scr, and bit p31ddr. te 0 1 p31ddr 0 1 pin function p3 1 input pin p3 1 output pin * txd1 output pin note: * when p31odr = 1, the pin becomes an nmos open-drain output. p3 0 /txd0 the pin function is switched as shown below according to the combination of bit te in the sci0 scr, and bit p30ddr. te 0 1 p30ddr 0 1 pin function p3 0 input pin p3 0 output pin * txd0 output pin note: * when p30odr = 1, the pin becomes an nmos open-drain output. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
225 8.5 port 4 8.5.1 overview port 4 is an 8-bit input-only port. port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0 and da1) in the h8s/2355 and h8s/2353, and as a/d converter analog input pins (an0 to an7) in the h8s/2393. port 4 pin functions are the same in all operating modes. figure 8-4 shows the port 4 pin configuration. p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 note: * as the h8s/2393 does not support a d/a converter, it does not have the da0 and da1 outputs. (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ an7 (input)/da1 * (output) an6 (input)/da0 * (output) an5 (input) an4 (input) an3 (input) an2 (input) an1 (input) an0 (input) port 4 pins port 4 figure 8-4 port 4 pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
226 8.5.2 register configuration table 8-8 shows the port 4 register configuration. port 4 is an input-only port, and does not have a data direction register or data register. table 8-8 port 4 registers name abbreviation r/w initial value address* port 4 register port4 r undefined h'ff53 note: * lower 16 bits of the address. port 4 register (port4): the pin states are always read when a port 4 read is performed. 7 p47 * r 6 p46 * r 5 p45 * r 4 p44 * r 3 p43 * r 0 p40 * r 2 p42 * r 1 p41 * r bit initial value r/w : : : note: * determined by state of pins p4 7 to p4 0 . 8.5.3 pin functions h8s/2355 and h8s/2353 port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0 and da1). h8s/2393 port 4 pins also function as a/d converter analog input pins (an0 to an7). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
227 8.6 port 5 8.6.1 overview port 5 is a 4-bit i/o port. port 5 pins also function as sci i/o pins (txd2, rxd2, and sck2) and the a/d converter input pin ( adtrg ). port 5 pin functions are the same in all operating modes. figure 8-5 shows the port 5 pin configuration. p5 3 p5 2 p5 1 p5 0 (i/o)/ (i/o)/ (i/o)/ (i/o)/ adtrg sck2 rxd2 txd2 (input) (i/o) (input) (output) port 5 pins port 5 figure 8-5 port 5 pin functions 8.6.2 register configuration table 8-9 shows the port 5 register configuration. table 8-9 port 5 registers name abbreviation r/w initial value * 2 address * 1 port 5 data direction register p5ddr w h'0 h'feb4 port 5 data register p5dr r/w h'0 h'ff64 port 5 register port5 r undefined h'ff54 notes: 1. lower 16 bits of the address. 2. value of bits 3 to 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
228 port 5 data direction register (p5ddr) 7 undefined 6 undefined 5 undefined 4 undefined 3 p53ddr 0 w 0 p50ddr 0 w 2 p52ddr 0 w 1 p51ddr 0 w bit initial value r/w : : : p5ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. bits 7 to 4 are reserved. p5ddr cannot be read; if it is, an undefined value will be read. setting a p5ddr bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p5ddr is initialized to h'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. as the sci is initialized, the pin states are determined by the p5ddr and p5dr specifications. port 5 data register (p5dr) 7 undefined 6 undefined 5 undefined 4 undefined 3 p53dr 0 r/w 0 p50dr 0 r/w 2 p52dr 0 r/w 1 p51dr 0 r/w bit initial value r/w : : : p5dr is an 8-bit readable/writable register that stores output data for the port 5 pins (p5 3 to p5 0 ). bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. p5dr is initialized to h'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
229 port 5 register (port5) 7 undefined 6 undefined 5 undefined 4 undefined 3 p53 * r 0 p50 * r 2 p52 * r 1 p51 * r bit initial value r/w : : : note: * determined by state of pins p5 3 to p5 0 . port5 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 5 pins (p5 3 to p5 0 ) must always be performed on p5dr. bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. if a port 5 read is performed while p5ddr bits are set to 1, the p5dr values are read. if a port 5 read is performed while p5ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port5 contents are determined by the pin states, as p5ddr and p5dr are initialized. port5 retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
230 8.6.3 pin functions port 5 pins also function as sci i/o pins (txd2, rxd2, and sck2), and the a/d converter input pin ( adtrg ). port 5 pin functions are shown in table 8-10. table 8-10 port 5 pin functions pin selection method and pin functions p5 3 / adtrg the pin function is switched as shown below according to the combination of bits trgs1 and trgs0 in the a/d converter adcr, and bit p53ddr. p53ddr 0 1 pin function p5 3 input pin p5 3 output pin adtrg input pin * note: * adtrg input when trgs0 = trgs1 = 1. p5 2 /sck2 the pin function is switched as shown below according to the combination of bit c/ a in the sci2 smr, bits cke0 and cke1 in scr, and bit p52ddr. cke1 0 1 c/ a 01 cke0 0 1 p52ddr 0 1 pin function p5 2 input pin p5 2 output pin sck2 output pin sck2 output pin sck2 input pin p5 1 /rxd2 the pin function is switched as shown below according to the combination of bit re in the sci2 scr, and bit p51ddr. re 0 1 p51ddr 0 1 pin function p5 1 input pin p5 1 output pin rxd2 input pin p5 0 /txd2 the pin function is switched as shown below according to the combination of bit te in the sci2 scr, and bit p50ddr. te 0 1 p50ddr 0 1 pin function p5 0 input pin p5 0 output pin txd2 output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
231 8.7 port 6 8.7.1 overview port 6 is an 8-bit i/o port. port 6 pins also function as interrupt input pins ( irq0 to irq3 ) and bus control output pins ( cs4 to cs7 ). the functions of pins p6 5 to p6 2 are the same in all operating modes, while the functions of pins p6 7 , p6 6 , p6 1 , and p6 0 change according to the operating mode. pins p6 7 to p6 4 are schmitt-triggered inputs. figure 8-6 shows the port 6 pin configuration. p6 7 / irq3 / cs7 p6 6 / irq2 / cs6 p6 5 / irq1 p6 4 / irq0 p6 3 p6 2 p6 1 / cs5 p6 0 / cs4 p6 7 (i/o)/ irq3 (input) p6 6 (i/o)/ irq2 (input) p6 5 (i/o)/ irq1 (input) p6 4 (i/o)/ irq0 (input) p6 3 (i/o) p6 2 (i/o) p6 1 (i/o) p6 0 (i/o) port 6 pins pin functions in modes 1, 2, 3, and 7 p6 7 (input)/ irq3 (input)/ cs7 (output) p6 6 (input)/ irq2 (input)/ cs6 (output) p6 5 (i/o)/ irq1 (input) p6 4 (i/o)/ irq0 (input) p6 3 (i/o) p6 2 (i/o) p6 1 (input)/ cs5 (output) p6 0 (input)/ cs4 (output) pin functions in modes 4 to 6 port 6 figure 8-6 port 6 pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
232 8.7.2 register configuration table 8-11 shows the port 6 register configuration. table 8-11 port 6 registers name abbreviation r/w initial value address * port 6 data direction register p6ddr w h'00 h'feb5 port 6 data register p6dr r/w h'00 h'ff65 port 6 register port6 r undefined h'ff55 note: * lower 16 bits of the address. port 6 data direction register (p6ddr) 7 p67ddr 0 w 6 p66ddr 0 w 5 p65ddr 0 w 4 p64ddr 0 w 3 p63ddr 0 w 0 p60ddr 0 w 2 p62ddr 0 w 1 p61ddr 0 w bit initial value r/w : : : p6ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. p6ddr cannot be read; if it is, an undefined value will be read. setting a p6ddr bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p6ddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
233 port 6 data register (p6dr) 7 p67dr 0 r/w 6 p66dr 0 r/w 5 p65dr 0 r/w 4 p64dr 0 r/w 3 p63dr 0 r/w 0 p60dr 0 r/w 2 p62dr 0 r/w 1 p61dr 0 r/w bit initial value r/w : : : p6dr is an 8-bit readable/writable register that stores output data for the port 6 pins (p6 7 to p6 0 ). p6dr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port 6 register (port6) 7 p67 * r 6 p66 * r 5 p65 * r 4 p64 * r 3 p63 * r 0 p60 * r 2 p62 * r 1 p61 * r bit initial value rw : : : note: * determined by state of pins p6 7 to p6 0 . port6 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 6 pins (p6 7 to p6 0 ) must always be performed on p6dr. if a port 6 read is performed while p6ddr bits are set to 1, the p6dr values are read. if a port 6 read is performed while p6ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port6 contents are determined by the pin states, as p6ddr and p6dr are initialized. port6 retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
234 8.7.3 pin functions port 6 pins also function as interrupt input pins ( irq0 to irq3 ) and bus control output pins ( cs4 to cs7 ). port 6 pin functions are shown in table 8-12. table 8-12 port 6 pin functions pin selection method and pin functions p6 7 / irq3 / cs7 the pin function is switched as shown below according to bit p67ddr. mode modes 1, 2, 3, 7 modes 4 to 6 p67ddr 0 1 0 1 pin function p6 7 input pin p6 7 output pin p6 7 input pin cs7 output pin irq3 interrupt input pin p6 6 / irq2 / cs6 the pin function is switched as shown below according to bit p66ddr. mode modes 1, 2, 3, 7 modes 4 to 6 p66ddr 0 1 0 1 pin function p6 6 input pin p6 6 output pin p6 6 input pin cs6 output pin irq2 interrupt input pin p6 5 / irq1 the pin function is switched as shown below according to bit p65ddr. p65ddr 0 1 pin function p6 5 input pin p6 5 output pin irq1 interrupt input pin p6 4 / irq0 the pin function is switched as shown below according to bit p64ddr. p64ddr 0 1 pin function p6 4 input pin p6 4 output pin irq0 interrupt input pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
235 pin selection method and pin functions p6 3 the pin function is switched as shown below according to bit p63ddr. p63ddr 0 1 pin function p6 3 input pin p6 3 output pin p6 2 the pin function is switched as shown below according to bit p62ddr. p62ddr 0 1 pin function p6 2 input pin p6 2 output pin p6 1 / cs5 the pin function is switched as shown below according to bit p61ddr. mode modes 1, 2, 3, 7 modes 4 to 6 p61ddr 0 1 0 1 pin function p6 1 input pin p6 1 output pin p6 1 input pin cs5 output pin p6 0 / cs4 the pin function is switched as shown below according to bit p60ddr. mode modes 1, 2, 3, 7 modes 4 to 6 p60ddr 0 1 0 1 pin function p6 0 input pin p6 0 output pin p6 0 input pin cs4 output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
236 8.8 port a 8.8.1 overview port a is an 8-bit i/o port. port a pins also function as address bus outputs and interrupt input pins ( irq4 to irq7 ). the pin functions change according to the operating mode. port a has a built-in mos input pull-up function that can be controlled by software. pins pa 7 to pa 4 are schmitt-triggered inputs. figure 8-7 shows the port a pin configuration. pa 7 /a 23 / irq7 pa 6 /a 22 / irq6 pa 5 /a 21 / irq5 pa 4 /a 20 / irq4 pa 3 /a 19 pa 2 /a 18 pa 1 /a 17 pa 0 /a 16 pa 7 (input)/a 23 (output)/ irq7 (input) pa 6 (input)/a 22 (output)/ irq6 (input) pa 5 (input)/a 21 (output)/ irq5 (input) a 20 (output) a 19 (output) a 18 (output) a 17 (output) a 16 (output) port a pins pin functions in modes 4 and 5 pin functions in mode 6 pa 7 (i/o)/ irq7 (input) pa 6 (i/o)/ irq6 (input) pa 5 (i/o)/ irq5 (input) pa 4 (i/o)/ irq4 (input) pa 3 (i/o) pa 2 (i/o) pa 1 (i/o) pa 0 (i/o) pin functions in modes 1, 2, 3, and 7 pa 7 (input)/a 23 (output)/ irq7 (input) pa 6 (input)/a 22 (output)/ irq6 (input) pa 5 (input)/a 21 (output)/ irq5 (input) pa 4 (input)/a 20 (output)/ irq4 (input) pa 3 (input)/a 19 (output) pa 2 (input)/a 18 (output) pa 1 (input)/a 17 (output) pa 0 (input)/a 16 (output) port a figure 8-7 port a pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
237 8.8.2 register configuration table 8-13 shows the port a register configuration. table 8-13 port a registers name abbreviation r/w initial value address * port a data direction register paddr w h'00 h'feb9 port a data register padr r/w h'00 h'ff69 port a register porta r undefined h'ff59 port a mos pull-up control register papcr r/w h'00 h'ff70 port a open-drain control register paodr r/w h'00 h'ff77 note: * lower 16 bits of the address. port a data direction register (paddr) 7 pa7ddr 0 w 6 pa6ddr 0 w 5 pa5ddr 0 w 4 pa4ddr 0 w 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit initial value r/w : : : paddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port a. paddr cannot be read; if it is, an undefined value will be read. paddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. modes 1, 2, 3, and 7 setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. modes 4 and 5 the corresponding port a pins are address outputs irrespective of the value of bits pa4ddr to pa0ddr. setting one of bits pa7ddr to pa5ddr to 1 makes the corresponding port a pin an address output, while clearing the bit to 0 makes the pin an input port. mode 6 setting a paddr bit to 1 makes the corresponding port a pin an address output while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
238 port a data register (padr) 7 pa7dr 0 r/w 6 pa6dr 0 r/w 5 pa5dr 0 r/w 4 pa4dr 0 r/w 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w bit initial value r/w : : : padr is an 8-bit readable/writable register that stores output data for the port a pins (pa 7 to pa 0 ). padr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port a register (porta) 7 pa7 * r 6 pa6 * r 5 pa5 * r 4 pa4 * r 3 pa3 * r 0 pa0 * r 2 pa2 * r 1 pa1 * r bit initial value r/w note: * determined by state of pins pa 7 to pa 0 . : : : porta is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port a pins (pa 7 to pa 0 ) must always be performed on padr. if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, porta contents are determined by the pin states, as paddr and padr are initialized. porta retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
239 port a mos pull-up control register (papcr) 7 pa7pcr 0 r/w 6 pa6pcr 0 r/w 5 pa5pcr 0 r/w 4 pa4pcr 0 r/w 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w bit initial value r/w : : : papcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port a on an individual bit basis. all the bits are valid in modes 1, 2, 3, 6, and 7, and bits 7 to 5 are valid in modes 4 and 5. when a paddr bit is cleared to 0 (input port setting), setting the corresponding papcr bit to 1 turns on the mos input pull-up for the corresponding pin. papcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port a open drain control register (paodr) 7 pa7odr 0 r/w 6 pa6odr 0 r/w 5 pa5odr 0 r/w 4 pa4odr 0 r/w 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w bit initial value r/w : : : paodr is an 8-bit readable/writable register that controls whether pmos is on or off for each port a pin (pa 7 to pa 0 ). all bits are valid in modes 1, 2, 3, and 7. setting a paodr bit to 1 makes the corresponding port a pin an nmos open-drain output, while clearing the bit to 0 makes the pin a cmos output. paodr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
240 8.8.3 pin functions modes 1, 2, 3 and 7: in mode 1, 2, 3, and 7, port a pins function as i/o ports and interrupt input pins. input or output can be specified for each pin on an individual bit basis. setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. port a pin functions in modes 1, 2, 3, and 7 are shown in figure 8-8. pa 7 (i/o)/ irq7 (input) pa 6 (i/o)/ irq6 (input) pa 5 (i/o)/ irq5 (input) pa 4 (i/o)/ irq4 (input) pa 3 (i/o) pa 2 (i/o) pa 1 (i/o) pa 0 (i/o) port a figure 8-8 port a pin functions (modes 1, 2, 3, and 7) modes 4 and 5: in modes 4 and 5, the lower 5 bits of port a are designated as address outputs automatically, while the upper 3 bits function as address outputs or input ports and interrupt input pins. input or output can be specified individually for the upper 3 bits. setting one of bits pa7ddr to pa5ddr to 1 makes the corresponding port a pin an address output, while clearing the bit to 0 makes the pin an input port. port a pin functions in modes 4 and 5 are shown in figure 8-9. a 23 (output) a 22 (output) a 21 (output) a 20 (output) a 19 (output) a 18 (output) a 17 (output) a 16 (output) pa 7 (input)/ irq7 (input) pa 6 (input)/ irq6 (input) pa 5 (input)/ irq5 (input) a 20 (output) a 19 (output) a 18 (output) a 17 (output) a 16 (output) when paddr = 1 when paddr = 0 port a figure 8-9 port a pin functions (modes 4 and 5) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
241 mode 6: in mode 6, port a pins function as address outputs or input ports and interrupt input pins. input or output can be specified on an individual bit basis. setting a paddr bit to 1 makes the corresponding port a pin an address output, while clearing the bit to 0 makes the pin an input port. port a pin functions in mode 6 are shown in figure 8-10. a 23 (output) a 22 (output) a 21 (output) a 20 (output) a 19 (output) a 18 (output) a 17 (output) a 16 (output) pa 7 (input)/ irq7 (input) pa 6 (input)/ irq6 (input) pa 5 (input)/ irq5 (input) pa 4 (input)/ irq4 (input) pa 3 (input) pa 2 (input) pa 1 (input) pa 0 (input) when paddr = 1 when paddr = 0 port a figure 8-10 port a pin functions (mode 6) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
242 8.8.4 mos input pull-up function port a has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used by pins pa 7 to pa 5 in modes 4 and 5, and by all pins in modes 1, 2, 3, 6, and 7. mos input pull-up can be specified as on or off on an individual bit basis. when a paddr bit is cleared to 0, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained after a manual reset, and in software standby mode. table 8-14 summarizes the mos input pull-up states. table 8-14 mos input pull-up states (port a) modes power-on reset hardware standby mode manual reset software standby mode in other operations 1 to 3, 6, 7 pa 7 to pa 0 off on/off 4, 5 pa 7 to pa 5 on/off pa 4 to pa 0 off legend: off : mos input pull-up is always off. on/off : on when paddr = 0 and papcr = 1; otherwise off. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
243 8.9 port b 8.9.1 overview port b is an 8-bit i/o port. port b has an address bus output function, and the pin functions change according to the operating mode. port b has a built-in mos input pull-up function that can be controlled by software. figure 8-11 shows the port b pin configuration. pb 7 /a 15 pb 6 /a 14 pb 5 /a 13 pb 4 /a 12 pb 3 /a 11 pb 2 /a 10 pb 1 /a 9 pb 0 /a 8 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 (output) (output) (output) (output) (output) (output) (output) (output) port b pins pin functions in modes 2 and 6 pin functions in modes 3 and 7 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 (output) (output) (output) (output) (output) (output) (output) (output) pin functions in modes 1, 4, and 5 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port b figure 8-11 port b pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
244 8.9.2 register configuration table 8-15 shows the port b register configuration. table 8-15 port b registers name abbreviation r/w initial value address * port b data direction register pbddr w h'00 h'feba port b data register pbdr r/w h'00 h'ff6a port b register portb r undefined h'ff5a port b mos pull-up control register pbpcr r/w h'00 h'ff71 note: * lower 16 bits of the address. port b data direction register (pbddr) 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w bit initial value r/w : : : pbddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port b. pbddr cannot be read; if it is, an undefined value will be read. pbddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. modes 1, 4, and 5 the corresponding port b pins are address outputs irrespective of the value of the pbddr bits. modes 2 and 6 setting a pbddr bit to 1 makes the corresponding port b pin an address output, while clearing the bit to 0 makes the pin an input port. modes 3 and 7 setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
245 port b data register (pbdr) 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w bit initial value r/w : : : pbdr is an 8-bit readable/writable register that stores output data for the port b pins (pb 7 to pb 0 ). pbdr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port b register (portb) 7 pb7 * r 6 pb6 * r 5 pb5 * r 4 pb4 * r 3 pb3 * r 0 pb0 * r 2 pb2 * r 1 pb1 * r bit initial value r/w note: * determined by state of pins pb 7 to pb 0 . : : : portb is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port b pins (pb 7 to pb 0 ) must always be performed on pbdr. if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portb contents are determined by the pin states, as pbddr and pbdr are initialized. portb retains its prior state after a manual reset, and in software standby mode. port b mos pull-up control register (pbpcr) 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w bit initial value r/w : : : pbpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port b on an individual bit basis. when a pbddr bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for the corresponding pin. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
246 pbpcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. 8.9.3 pin functions modes 1, 4, and 5: in modes 1, 4, and 5, port b pins are automatically designated as address outputs. port b pin functions in modes 1, 4, and 5 are shown in figure 8-12. a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 (output) (output) (output) (output) (output) (output) (output) (output) port b figure 8-12 port b pin functions (modes 1, 4, and 5) modes 2 and 6: in modes 2 and 6, port b pins function as address outputs or input ports. input or output can be specified on an individual bit basis. setting a pbddr bit to 1 makes the corresponding port b pin an address output, while clearing the bit to 0 makes the pin an input port. port b pin functions in modes 2 and 6 are shown in figure 8-13. a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 (input) (input) (input) (input) (input) (input) (input) (input) when pbddr = 1 when pbddr = 0 (output) (output) (output) (output) (output) (output) (output) (output) port b figure 8-13 port b pin functions (modes 2 and 6) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
247 modes 3 and 7: in modes 3 and 7, port b pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. port b pin functions in modes 3 and 7 are shown in figure 8-14. pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 port b (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 8-14 port b pin functions (modes 3 and 7) 8.9.4 mos input pull-up function port b has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. when a pbddr bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained after a manual reset, and in software standby mode. table 8-16 summarizes the mos input pull-up states. table 8-16 mos input pull-up states (port b) modes power-on reset hardware standby mode manual reset software standby mode in other operations 1, 4, 5 off off 2, 3, 6, 7 on/off legend: off : mos input pull-up is always off. on/off : on when pbddr = 0 and pbpcr = 1; otherwise off. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
248 8.10 port c 8.10.1 overview port c is an 8-bit i/o port. port c has an address bus output function, and the pin functions change according to the operating mode. port c has a built-in mos input pull-up function that can be controlled by software. figure 8-15 shows the port c pin configuration. pc 7 /a 7 pc 6 /a 6 pc 5 /a 5 pc 4 /a 4 pc 3 /a 3 pc 2 /a 2 pc 1 /a 1 pc 0 /a 0 port c pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ (input)/ a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 (output) (output) (output) (output) (output) (output) (output) (output) port c pins pin functions in modes 2 and 6 pin functions in modes 3 and 7 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 (output) (output) (output) (output) (output) (output) (output) (output) pin functions in modes 1, 4, and 5 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 8-15 port c pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
249 8.10.2 register configuration table 8-17 shows the port c register configuration. table 8-17 port c registers name abbreviation r/w initial value address * port c data direction register pcddr w h'00 h'febb port c data register pcdr r/w h'00 h'ff6b port c register portc r undefined h'ff5b port c mos pull-up control register pcpcr r/w h'00 h'ff72 note: * lower 16 bits of the address. port c data direction register (pcddr) 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w bit initial value r/w : : : pcddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port c. pcddr cannot be read; if it is, an undefined value will be read. pcddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. modes 1, 4, and 5 the corresponding port c pins are address outputs irrespective of the value of the pcddr bits. modes 2 and 6 setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. modes 3 and 7 setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
250 port c data register (pcdr) 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w bit initial value r/w : : : pcdr is an 8-bit readable/writable register that stores output data for the port c pins (pc 7 to pc 0 ). pcdr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port c register (portc) 7 pc7 * r 6 pc6 * r 5 pc5 * r 4 pc4 * r 3 pc3 * r 0 pc0 * r 2 pc2 * r 1 pc1 * r bit initial value r/w note: * determined by state of pins pc 7 to pc 0 . : : : portc is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port c pins (pc 7 to pc 0 ) must always be performed on pcdr. if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portc contents are determined by the pin states, as pcddr and pcdr are initialized. portc retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
251 port c mos pull-up control register (pcpcr) 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w bit initial value r/w : : : pcpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port c on an individual bit basis. when a pcddr bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pcpcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. 8.10.3 pin functions modes 1, 4, and 5: in modes 1, 4, and 5, port c pins are automatically designated as address outputs. port c pin functions in modes 1, 4, and 5 are shown in figure 8-16. a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 (output) (output) (output) (output) (output) (output) (output) (output) port c figure 8-16 port c pin functions (modes 1, 4, and 5) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
252 modes 2 and 6: in modes 2 and 6, port c pins function as address outputs or input ports. input or output can be specified on an individual bit basis. setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. port c pin functions in modes 2 and 6 are shown in figure 8-17. a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 port c pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 (input) (input) (input) (input) (input) (input) (input) (input) when pcddr = 1 when pcddr = 0 (output) (output) (output) (output) (output) (output) (output) (output) figure 8-17 port c pin functions (modes 2 and 6) modes 3 and 7: in modes 3 and 7, port c pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. port c pin functions in modes 3 and 7 are shown in figure 8-18. pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 port c (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 8-18 port c pin functions (modes 3 and 7) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
253 8.10.4 mos input pull-up function port c has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. when a pcddr bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained after a manual reset, and in software standby mode. table 8-18 summarizes the mos input pull-up states. table 8-18 mos input pull-up states (port c) modes power-on reset hardware standby mode manual reset software standby mode in other operations 1, 4, 5 off off 2, 3, 6, 7 on/off legend: off : mos input pull-up is always off. on/off : on when pcddr = 0 and pcpcr = 1; otherwise off. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
254 8.11 port d 8.11.1 overview port d is an 8-bit i/o port. port d has a data bus i/o function, and the pin functions change according to the operating mode. port d has a built-in mos input pull-up function that can be controlled by software. figure 8-19 shows the port d pin configuration. pd 7 /d 15 pd 6 /d 14 pd 5 /d 13 pd 4 /d 12 pd 3 /d 11 pd 2 /d 10 pd 1 /d 9 pd 0 /d 8 port d d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port d pins pin functions in modes 1, 2, 4, 5, and 6 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pin functions in modes 3 and 7 figure 8-19 port d pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
255 8.11.2 register configuration table 8-19 shows the port d register configuration. table 8-19 port d registers name abbreviation r/w initial value address * port d data direction register pdddr w h'00 h'febc port d data register pddr r/w h'00 h'ff6c port d register portd r undefined h'ff5c port d mos pull-up control register pdpcr r/w h'00 h'ff73 note: * lower 16 bits of the address. port d data direction register (pdddr) 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit initial value r/w : : : pdddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port d. pdddr cannot be read; if it is, an undefined value will be read.. pdddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. modes 1, 2, 4, 5, and 6 the input/output direction specification by pdddr is ignored, and port d is automatically designated for data i/o. modes 3 and 7 setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
256 port d data register (pddr) 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 0 pd0dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w bit initial value r/w : : : pddr is an 8-bit readable/writable register that stores output data for the port d pins (pd 7 to pd 0 ). pddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port d register (portd) 7 pd7 * r 6 pd6 * r 5 pd5 * r 4 pd4 * r 3 pd3 * r 0 pd0 * r 2 pd2 * r 1 pd1 * r bit initial value r/w note: * determined by state of pins pd 7 to pd 0 . : : : portd is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port d pins (pd 7 to pd 0 ) must always be performed on pddr. if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portd contents are determined by the pin states, as pdddr and pddr are initialized. portd retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
257 port d mos pull-up control register (pdpcr) 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w bit initial value r/w : : : pdpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port d on an individual bit basis. when a pdddr bit is cleared to 0 (input port setting) in mode 3 or 7, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pdpcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. 8.11.3 pin functions modes 1, 2, 4, 5, and 6: in modes 1, 2, 4, 5, and 6, port d pins are automatically designated as data i/o pins. port d pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 8-20. d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 port d (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 8-20 port d pin functions (modes 1, 2, 4, 5, and 6) modes 3 and 7: in modes 3 and 7, port d pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
258 port d pin functions in modes 3 and 7 are shown in figure 8-21. pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 port d (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 8-21 port d pin functions (modes 3 and 7) 8.11.4 mos input pull-up function port d has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 3 and 7, and can be specified as on or off on an individual bit basis. when a pdddr bit is cleared to 0 in mode 3 or 7, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained after a manual reset, and in software standby mode. table 8-20 summarizes the mos input pull-up states. table 8-20 mos input pull-up states (port d) modes power-on reset hardware standby mode manual reset software standby mode in other operations 1, 2, 4 to 6 off off 3, 7 on/off legend: off : mos input pull-up is always off. on/off : on when pdddr = 0 and pdpcr = 1; otherwise off. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
259 8.12 port e 8.12.1 overview port e is an 8-bit i/o port. port e has a data bus i/o function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. port e has a built-in mos input pull-up function that can be controlled by software. figure 8-22 shows the port e pin configuration. pe 7 /d 7 pe 6 /d 6 pe 5 /d 5 pe 4 /d 4 pe 3 /d 3 pe 2 /d 2 pe 1 /d 1 pe 0 /d 0 pe 7 pe 6 pe 5 pe 4 pe 3 pe 2 pe 1 pe 0 (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ port e pins pin functions in modes 1, 2, 4, 5, and 6 pin functions in modes 3 and 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pe 7 pe 6 pe 5 pe 4 pe 3 pe 2 pe 1 pe 0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port e figure 8-22 port e pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
260 8.12.2 register configuration table 8-21 shows the port e register configuration. table 8-21 port e registers name abbreviation r/w initial value address * port e data direction register peddr w h'00 h'febd port e data register pedr r/w h'00 h'ff6d port e register porte r undefined h'ff5d port e mos pull-up control register pepcr r/w h'00 h'ff74 note: * lower 16 bits of the address. port e data direction register (peddr) 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w bit initial value r/w : : : peddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port e. peddr cannot be read; if it is, an undefined value will be read. peddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. modes 1, 2, 4, 5, and 6 when 8-bit bus mode has been selected, port e pins function as i/o ports. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode has been selected, the input/output direction specification by peddr is ignored, and port e is designated for data i/o. for details of 8-bit and 16-bit bus modes, see section 6, bus controller. modes 3 and 7 setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
261 port e data register (pedr) 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w bit initial value r/w : : : pedr is an 8-bit readable/writable register that stores output data for the port e pins (pe 7 to pe 0 ). pedr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port e register (porte) 7 pe7 * r 6 pe6 * r 5 pe5 * r 4 pe4 * r 3 pe3 * r 0 pe0 * r 2 pe2 * r 1 pe1 * r bit initial value r/w note: * determined by state of pins pe 7 to pe 0 . : : : porte is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port e pins (pe 7 to pe 0 ) must always be performed on pedr. if a port e read is performed while peddr bits are set to 1, the pedr values are read. if a port e read is performed while peddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, porte contents are determined by the pin states, as peddr and pedr are initialized. porte retains its prior state after a manual reset, and in software standby mode. port e mos pull-up control register (pepcr) 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w bit initial value r/w : : : pepcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port e on an individual bit basis. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
262 when a peddr bit is cleared to 0 (input port setting) when 8-bit bus mode is selected in mode 1, 2, 4, 5, or 6, or in mode 3 or 7, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for the corresponding pin. pepcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. 8.12.3 pin functions modes 1, 2, 4, 5, and 6: in modes 1, 2, 4, 5, and 6, when 8-bit access is designated and 8-bit bus mode is selected, port e pins are automatically designated as i/o ports. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction specification by peddr is ignored, and port e is designated for data i/o. port e pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 8-23. pe 7 pe 6 pe 5 pe 4 pe 3 pe 2 pe 1 pe 0 port e d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) 8-bit bus mode 16-bit bus mode (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 8-23 port e pin functions (modes 1, 2, 4, 5, and 6) modes 3 and 7: in modes 3 and 7, port e pins function as i/o ports. input or output can be specified for each pin on a bit-by-bit basis. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
263 port e pin functions in modes 3 and 7 are shown in figure 8-24. pe 7 pe 6 pe 5 pe 4 pe 3 pe 2 pe 1 pe 0 port e (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 8-24 port e pin functions (modes 3 and 7) 8.12.4 mos input pull-up function port e has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 1, 2, 4, 5, and 6 when 8-bit bus mode is selected, or in mode 3 or 7, and can be specified as on or off on an individual bit basis. when a peddr bit is cleared to 0 in mode 1, 2, 4, 5, or 6 when 8-bit bus mode is selected, or in mode 3 or 7, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained after a manual reset, and in software standby mode. table 8-22 summarizes the mos input pull-up states. table 8-22 mos input pull-up states (port e) modes power-on reset hardware standby mode manual reset software standby mode in other operations 3, 7 off on/off 1, 2, 4 to 6 8-bit bus 16-bit bus off legend: off : mos input pull-up is always off. on/off : on when peddr = 0 and pepcr = 1; otherwise off. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
264 8.13 port f 8.13.1 overview port f is an 8-bit i/o port. port f pins also function as bus control signal input/output pins ( as , rd , hwr , lwr , wait , breq , and back ) and the system clock (?) output pin. figure 8-25 shows the port f pin configuration. pf 7 / pf 6 / as pf 5 / rd pf 4 / hwr pf 3 / lwr pf 2 / wait pf 1 / back pf 0 / breq port f pf 7 (input)/?(output) as (output) rd (output) hwr (output) lwr (output) pf 2 (i/o)/ wait (input) pf 1 (i/o)/ back (output) pf 0 (i/o)/ breq (input) port f pins pin functions in modes 1, 2, 4, 5, and 6 pf 7 (input)/?(output) pf 6 (i/o) pf 5 (i/o) pf 4 (i/o) pf 3 (i/o) pf 2 (i/o) pf 1 (i/o) pf 0 (i/o) pin functions in modes 3 and 7 figure 8-25 port f pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
265 8.13.2 register configuration table 8-23 shows the port f register configuration. table 8-23 port f registers name abbreviation r/w initial value address * 1 port f data direction register pfddr w h'80/h'00 * 2 h'febe port f data register pfdr r/w h'00 h'ff6e port f register portf r undefined h'ff5e notes: 1. lower 16 bits of the address. 2. initial value depends on the mode. port f data direction register (pfddr) 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w bit modes 1, 2, 4, 5, 6 initial value r/w modes 3 and 7 initial value r/w : : : : : pfddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port f. pfddr cannot be read; if it is, an undefined value will be read. pfddr is initialized by a power-on reset, and in hardware standby mode, to h'80 in modes 1, 2, 4, 5, and 6, and to h'00 in modes 3 and 7. it retains its prior state after a manual reset, and in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. modes 1, 2, 4, 5, and 6 pin pf 7 functions as the ? output pin when the corresponding pfddr bit is set to 1, and as an input port when the bit is cleared to 0. the input/output direction specified by pfddr is ignored for pins pf 6 to pf 3 , which are automatically designated as bus control outputs ( as , rd , hwr , and lwr ). pins pf 2 to pf 0 are designated as bus control input/output pins ( wait , back , breq ) by means of bus controller settings. at other times, setting a pfddr bit to 1 makes the corresponding port f pin an output port, while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
266 modes 3 and 7 setting a pfddr bit to 1 makes the corresponding port f pin pf 6 to pf 0 an output port, or in the case of pin pf 7 , the ? output pin. clearing the bit to 0 makes the pin an input port. port f data register (pfdr) 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w bit initial value r/w : : : pfdr is an 8-bit readable/writable register that stores output data for the port f pins (pf 7 to pf 0 ). pfdr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port f register (portf) 7 pf7 * r 6 pf6 * r 5 pf5 * r 4 pf4 * r 3 pf3 * r 0 pf0 * r 2 pf2 * r 1 pf1 * r bit initial value r/w note: * determined by state of pins pf 7 to pf 0 . : : : portf is an 8-bit read-only register that shows the pin states. writing of output data for the port f pins (pf 7 to pf 0 ) must always be performed on pfdr. if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portf contents are determined by the pin states, as pfddr and pfdr are initialized. portf retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
267 8.13.3 pin functions port f pins also function as bus control signal input/output pins ( as , rd , hwr , lwr , wait , breq , and back ) and the system clock (?) output pin. the pin functions differ between modes 1, 2, 4, 5, and 6, and modes 3 and 7. port f pin functions are shown in table 8-24. table 8-24 port f pin functions pin selection method and pin functions pf 7 /? the pin function is switched as shown below according to bit pf7ddr. pf7ddr 0 1 pin function pf 7 input pin ? output pin pf 6 / as the pin function is switched as shown below according to the operating mode and bit pf6ddr. operating mode modes 1, 2, 4, 5, 6 modes 3 and 7 pf6ddr 0 1 pin function as output pin pf 6 input pin pf 6 output pin pf 5 / rd the pin function is switched as shown below according to the operating mode and bit pf5ddr. operating mode modes 1, 2, 4, 5, 6 modes 3 and 7 pf5ddr 0 1 pin function rd output pin pf 5 input pin pf 5 output pin pf 4 / hwr the pin function is switched as shown below according to the operating mode and bit pf4ddr. operating mode modes 1, 2, 4, 5, 6 modes 3 and 7 pf4ddr 0 1 pin function hwr output pin pf 4 input pin pf 4 output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
268 pin selection method and pin functions pf 3 / lwr the pin function is switched as shown below according to the operating mode and bit pf3ddr. operating mode modes 1, 2, 4, 5, 6 modes 3 and 7 pf3ddr 0 1 pin function lwr output pin pf 3 input pin pf 3 output pin pf 2 / wait the pin function is switched as shown below according to the combination of the operating mode, and bits waite and pf2ddr. operating mode modes 1, 2, 4, 5, 6 modes 3 and 7 waite 0 1 pf2ddr 0 1 0 1 pin function pf 2 input pin pf 2 output pin wait input pin pf 2 input pin pf 2 output pin note: * only when rmts2 to rmts0 = b'001 to b'011 and cw2 = 0 in modes 4 to 6. pf 1 / back the pin function is switched as shown below according to the combination of the operating mode, and bits brle and pf1ddr. operating mode modes 1, 2, 4, 5, 6 modes 3 and 7 brle 0 1 pf1ddr 0 1 0 1 pin function pf 1 input pin pf 1 output pin back output pin pf 1 input pin pf 1 output pin pf 0 / breq the pin function is switched as shown below according to the combination of the operating mode, and bits brle and pf0ddr. operating mode modes 1, 2, 4, 5, 6 modes 3 and 7 brle 0 1 pf0ddr 0 1 0 1 pin function pf 0 input pin pf 0 output pin breq input pin pf 0 input pin pf 0 output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
269 8.14 port g 8.14.1 overview port g is a 5-bit i/o port. port g pins also function as bus control signal output pins ( cs0 to cs3 , cas , and oe ). figure 8-26 shows the port g pin configuration. pg 4 / cs0 pg 3 / cs1 pg 2 / cs2 pg 1 / cs3 pg 0 pg 4 (i/o) pg 3 (i/o) pg 2 (i/o) pg 1 (i/o) pg 0 (i/o) port g pins pin functions in modes 3 and 7 pin functions in modes 4 to 6 pg 4 (input)/ cs0 (output) pg 3 (i/o) pg 2 (i/o) pg 1 (i/o) pg 0 (i/o) pin functions in modes 1 and 2 pg 4 (input)/ cs0 (output) pg 3 (input)/ cs1 (output) pg 2 (input)/ cs2 (output) pg 1 (input)/ cs3 (output) pg 0 (i/o) port g figure 8-26 port g pin functions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
270 8.14.2 register configuration table 8-25 shows the port g register configuration. table 8-25 port g registers name abbreviation r/w initial value * 2 address * 1 port g data direction register pgddr w h'10/h'00 * 3 h'febf port g data register pgdr r/w h'00 h'ff6f port g register portg r undefined h'ff5f notes: 1. lower 16 bits of the address. 2. value of bits 4 to 0. 3. initial value depends on the mode. port g data direction register (pgddr) 7 undefined undefined 6 undefined undefined 5 undefined undefined 4 pg4ddr 1 w 0 w 3 pg3ddr 0 w 0 w 0 pg0ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w bit modes 1, 4, 5 initial value r/w modes 2, 3, 6, 7 initial value r/w : : : : : pgddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port g. pgddr cannot be read, and bits 7 to 5 are reserved. if pgddr is read, an undefined value will be read. the pgddr4 bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes 1, 4, and 5, and to 0 in modes 2, 3, 6, and 7. it retains its prior state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. modes 1 and 2 pin pg 4 functions as a bus control output pin ( cs0 ) when the corresponding pgddr bit is set to 1, and as an input port when the bit is cleared to 0. for pins pg 3 to pg 0 , setting the corresponding pgddr bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
271 modes 3 and 7 setting a pgddr bit to 1 makes the corresponding port g pin an output port, while clearing the bit to 0 makes the pin an input port. modes 4, 5, and 6 pins pg 4 to pg 1 function as bus control output pins ( cs0 to cs3 ) when the corresponding pgddr bits are set to 1, and as input ports when the bits are cleared to 0. port g data register (pgdr) 7 undefined 6 undefined 5 undefined 4 pg4dr 0 r/w 3 pg3dr 0 r/w 0 pg0dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w bit initial value r/w : : : pgdr is an 8-bit readable/writable register that stores output data for the port g pins (pg 4 to pg 0 ). bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. pgdr is initialized to h'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. it retains its prior state after a manual reset, and in software standby mode. port g register (portg) 7 undefined 6 undefined 5 undefined 4 pg4 * r 3 pg3 * r 0 pg0 * r 2 pg2 * r 1 pg1 * r bit initial value r/w note: * determined by state of pins pg 4 to pg 0 . : : : portg is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port g pins (pg 4 to pg 0 ) must always be performed on pgdr. bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. if a port g read is performed while pgddr bits are set to 1, the pgdr values are read. if a port g read is performed while pgddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portg contents are determined by the pin states, as pgddr and pgdr are initialized. portg retains its prior state after a manual reset, and in software standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
272 8.14.3 pin functions port g pins also function as bus control signal output pins ( cs0 to cs3 , cas , and oe ). the pin functions are different in modes 1 and 2, modes 3 and 7, and modes 4 to 6. port g pin functions are shown in table 8-26. table 8-26 port g pin functions pin selection method and pin functions pg 4 / cs0 the pin function is switched as shown below according to the operating mode and bit pg4ddr. operating mode modes 1, 2, 4, 5, 6 modes 3 and 7 pg4ddr 0 1 0 1 pin function pg 4 input pin cs0 output pin pg 4 input pin pg 4 output pin pg 3 / cs1 the pin function is switched as shown below according to the operating mode and bit pg3ddr. operating mode modes 1, 2, 3, 7 modes 4 to 6 pg3ddr 0 1 0 1 pin function pg 3 input pin pg 3 output pin pg 3 input pin cs1 output pin pg 2 / cs2 the pin function is switched as shown below according to the operating mode and bit pg2ddr. operating mode modes 1, 2, 3, 7 modes 4 to 6 pg2ddr 0 1 0 1 pin function pg 2 input pin pg 2 output pin pg 2 input pin cs2 output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
273 pin selection method and pin functions pg 1 / cs3 the pin function is switched as shown below according to the operating mode and bit pg1ddr. operating mode modes 1, 2, 3, 7 modes 4 to 6 pg1ddr 0 1 0 1 pin function pg 1 input pin pg 1 output pin pg 1 input pin cs3 output pin pg 0 the pin function is switched as shown below according to the bit pg0ddr. pg0ddr 0 1 pin function pg 0 input pin pg 0 output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
275 section 9 16-bit timer pulse unit (tpu) 9.1 overview the h8s/2355 series has an on-chip 16-bit timer pulse unit (tpu) that comprises six 16-bit timer channels. 9.1.1 features maximum 16-pulse input/output ? a total of 16 timer general registers (tgrs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ? tgrc and tgrd for channels 0 and 3 can also be used as buffer registers selection of 8 counter input clocks for each channel the following operations can be set for each channel: ? waveform output at compare match: selection of 0, 1, or toggle output ? input capture function: selection of rising edge, falling edge, or both edge detection ? counter clear operation: counter clearing possible by compare match or input capture ? synchronous operation: multiple timer counters (tcnt) can be written to simultaneously simultaneous clearing by compare match and input capture possible register simultaneous input/output possible by counter synchronous operation ? pwm mode: any pwm output duty can be set maximum of 15-phase pwm output possible by combination with synchronous operation buffer operation settable for channels 0 and 3 ? input capture register double-buffering possible ? automatic rewriting of output compare register possible phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? two-phase encoder pulse up/down-count possible cascaded operation ? channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow fast access via internal 16-bit bus ? fast access is possible via a 16-bit bus interface www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
276 26 interrupt sources ? for channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ? for channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently automatic transfer of register data ? block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (dtc) activation a/d converter conversion start trigger can be generated ? channel 0 to 5 compare match a/input capture a signals can be used as a/d converter conversion start trigger module stop mode can be set ? as the initial setting, tpu operation is halted. register access is enabled by exiting module stop mode. table 9-1 lists the functions of the tpu. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
277 table 9-1 tpu functions item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 count clock ?/1 ?/4 ?/16 ?/64 tclka tclkb tclkc tclkd ?/1 ?/4 ?/16 ?/64 ?/256 tclka tclkb ?/1 ?/4 ?/16 ?/64 ?/1024 tclka tclkb tclkc ?/1 ?/4 ?/16 ?/64 ?/256 ?/1024 ?/4096 tclka ?/1 ?/4 ?/16 ?/64 ?/1024 tclka tclkc ?/1 ?/4 ?/16 ?/64 ?/256 tclka tclkc tclkd general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b tgr3a tgr3b tgr4a tgr4b tgr5a tgr5b general registers/ buffer registers tgr0c tgr0d tgr3c tgr3d i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture compare 0 output match 1 output output toggle output input capture function synchronous operation pwm mode phase counting mode buffer operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
278 item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture a/d converter trigger tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture tgr3a compare match or input capture tgr4a compare match or input capture tgr5a compare match or input capture interrupt sources 5 sources ? compare match or input capture 0a ? compare match or input capture 0b ? compare match or input capture 0c ? compare match or input capture 0d ? overflow 4 sources ? compare match or input capture 1a ? compare match or input capture 1b ? overflow ? underflow 4 sources ? compare match or input capture 2a ? compare match or input capture 2b ? overflow ? underflow 5 sources ? compare match or input capture 3a ? compare match or input capture 3b ? compare match or input capture 3c ? compare match or input capture 3d ? overflow 4 sources ? compare match or input capture 4a ? compare match or input capture 4b ? overflow ? underflow 4 sources ? compare match or input capture 5a ? compare match or input capture 5b ? overflow ? underflow legend : possible : not possible www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
279 9.1.2 block diagram figure 9-1 shows a block diagram of the tpu. channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb control logic tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd tsyr tstr input/output pins tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 clock input ?1 ?4 ?16 ?64 ?256 ?1024 ?4096 tclka tclkb tclkc tclkd input/output pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 3: channel 4: channel 5: interrupt request signals channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: channel 2 common channel 5 bus interface figure 9-1 block diagram of tpu 9.1.3 pin configuration table 9-2 summarizes the tpu pins. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
280 table 9-2 tpu pins channel name symbol i/o function all clock input a tclka input external clock a input pin (channel 1 and 5 phase counting mode a phase input) clock input b tclkb input external clock b input pin (channel 1 and 5 phase counting mode b phase input) clock input c tclkc input external clock c input pin (channel 2 and 4 phase counting mode a phase input) clock input d tclkd input external clock d input pin (channel 2 and 4 phase counting mode b phase input) 0 input capture/out compare match a0 tioca0 i/o tgr0a input capture input/output compare output/pwm output pin input capture/out compare match b0 tiocb0 i/o tgr0b input capture input/output compare output/pwm output pin input capture/out compare match c0 tiocc0 i/o tgr0c input capture input/output compare output/pwm output pin input capture/out compare match d0 tiocd0 i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/out compare match a1 tioca1 i/o tgr1a input capture input/output compare output/pwm output pin input capture/out compare match b1 tiocb1 i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/out compare match a2 tioca2 i/o tgr2a input capture input/output compare output/pwm output pin input capture/out compare match b2 tiocb2 i/o tgr2b input capture input/output compare output/pwm output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
281 channel name symbol i/o function 3 input capture/out compare match a3 tioca3 i/o tgr3a input capture input/output compare output/pwm output pin input capture/out compare match b3 tiocb3 i/o tgr3b input capture input/output compare output/pwm output pin input capture/out compare match c3 tiocc3 i/o tgr3c input capture input/output compare output/pwm output pin input capture/out compare match d3 tiocd3 i/o tgr3d input capture input/output compare output/pwm output pin 4 input capture/out compare match a4 tioca4 i/o tgr4a input capture input/output compare output/pwm output pin input capture/out compare match b4 tiocb4 i/o tgr4b input capture input/output compare output/pwm output pin 5 input capture/out compare match a5 tioca5 i/o tgr5a input capture input/output compare output/pwm output pin input capture/out compare match b5 tiocb5 i/o tgr5b input capture input/output compare output/pwm output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
282 9.1.4 register configuration table 9-3 summarizes the tpu registers. table 9-3 tpu registers channel name abbreviation r/w initial value address * 1 0 timer control register 0 tcr0 r/w h'00 h'ffd0 timer mode register 0 tmdr0 r/w h'c0 h'ffd1 timer i/o control register 0h tior0h r/w h'00 h'ffd2 timer i/o control register 0l tior0l r/w h'00 h'ffd3 timer interrupt enable register 0 tier0 r/w h'40 h'ffd4 timer status register 0 tsr0 r/(w) * 2 h'c0 h'ffd5 timer counter 0 tcnt0 r/w h'0000 h'ffd6 timer general register 0a tgr0a r/w h'ffff h'ffd8 timer general register 0b tgr0b r/w h'ffff h'ffda timer general register 0c tgr0c r/w h'ffff h'ffdc timer general register 0d tgr0d r/w h'ffff h'ffde 1 timer control register 1 tcr1 r/w h'00 h'ffe0 timer mode register 1 tmdr1 r/w h'c0 h'ffe1 timer i/o control register 1 tior1 r/w h'00 h'ffe2 timer interrupt enable register 1 tier1 r/w h'40 h'ffe4 timer status register 1 tsr1 r/(w) * 2 h'c0 h'ffe5 timer counter 1 tcnt1 r/w h'0000 h'ffe6 timer general register 1a tgr1a r/w h'ffff h'ffe8 timer general register 1b tgr1b r/w h'ffff h'ffea 2 timer control register 2 tcr2 r/w h'00 h'fff0 timer mode register 2 tmdr2 r/w h'c0 h'fff1 timer i/o control register 2 tior2 r/w h'00 h'fff2 timer interrupt enable register 2 tier2 r/w h'40 h'fff4 timer status register 2 tsr2 r/(w) * 2 h'c0 h'fff5 timer counter 2 tcnt2 r/w h'0000 h'fff6 timer general register 2a tgr2a r/w h'ffff h'fff8 timer general register 2b tgr2b r/w h'ffff h'fffa www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
283 channel name abbreviation r/w initial value address * 1 3 timer control register 3 tcr3 r/w h'00 h'fe80 timer mode register 3 tmdr3 r/w h'c0 h'fe81 timer i/o control register 3h tior3h r/w h'00 h'fe82 timer i/o control register 3l tior3l r/w h'00 h'fe83 timer interrupt enable register 3 tier3 r/w h'40 h'fe84 timer status register 3 tsr3 r/(w) * 2 h'c0 h'fe85 timer counter 3 tcnt3 r/w h'0000 h'fe86 timer general register 3a tgr3a r/w h'ffff h'fe88 timer general register 3b tgr3b r/w h'ffff h'fe8a timer general register 3c tgr3c r/w h'ffff h'fe8c timer general register 3d tgr3d r/w h'ffff h'fe8e 4 timer control register 4 tcr4 r/w h'00 h'fe90 timer mode register 4 tmdr4 r/w h'c0 h'fe91 timer i/o control register 4 tior4 r/w h'00 h'fe92 timer interrupt enable register 4 tier4 r/w h'40 h'fe94 timer status register 4 tsr4 r/(w) * 2 h'c0 h'fe95 timer counter 4 tcnt4 r/w h'0000 h'fe96 timer general register 4a tgr4a r/w h'ffff h'fe98 timer general register 4b tgr4b r/w h'ffff h'fe9a 5 timer control register 5 tcr5 r/w h'00 h'fea0 timer mode register 5 tmdr5 r/w h'c0 h'fea1 timer i/o control register 5 tior5 r/w h'00 h'fea2 timer interrupt enable register 5 tier5 r/w h'40 h'fea4 timer status register 5 tsr5 r/(w) * 2 h'c0 h'fea5 timer counter 5 tcnt5 r/w h'0000 h'fea6 timer general register 5a tgr5a r/w h'ffff h'fea8 timer general register 5b tgr5b r/w h'ffff h'feaa all timer start register tstr r/w h'00 h'ffc0 timer synchro register tsyr r/w h'00 h'ffc1 module stop control register mstpcr r/w h'3fff h'ff3c notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
284 9.2 register descriptions 9.2.1 timer control register (tcr) 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : channel 0: tcr0 channel 3: tcr3 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w channel 1: tcr1 channel 2: tcr2 channel 4: tcr4 channel 5: tcr5 bit initial value r/w : : : the tcr registers are 8-bit registers that control the tcnt channels. the tpu has six tcr registers, one for each of channels 0 to 5. the tcr registers are initialized to h'00 by a reset, and in hardware standby mode. tcr register settings should be made only when tcnt operation is stopped. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
285 bits 7, 6, 5counter clear 2, 1, and 0 (cclr2, cclr1, cclr0): these bits select the tcnt counter clearing source. bit 7 bit 6 bit 5 channel cclr2 cclr1 cclr0 description 0, 3 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 bit 7 bit 6 bit 5 channel reserved * 3 cclr1 cclr0 description 1, 2, 4, 5 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. bit 7 is reserved in channels 1, 2, 4, and 5. it is always read as 0 and cannot be modified. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
286 bits 4 and 3clock edge 1 and 0 (ckeg1, ckeg0): these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. ?/4 both edges = ?/2 rising edge). if phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. bit 4 bit 3 ckeg1 ckeg0 description 0 0 count at rising edge (initial value) 1 count at falling edge 1 count at both edges note: internal clock edge selection is valid when the input clock is ?/4 or slower. this setting is ignored if the input clock is ?/1, or when overflow/underflow of another channel is selected. bits 2, 1, and 0time prescaler 2, 1, and 0 (tpsc2 to tpsc0): these bits select the tcnt counter clock. the clock source can be selected independently for each channel. table 9-4 shows the clock sources that can be set for each channel. table 9-4 tpu clock sources channel internal clock ?/1 ?/4 ?/16 ?/64 ?/256 ?/1024 ?/4096 external clock tclka tclkb tclkc tclkd overflow/ underflow on another channel 0 1 2 3 4 5 legend : setting blank : no setting www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
287 bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 0000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 1000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on ?/256 1 counts on tcnt2 overflow/underflow note: this setting is ignored when channel 1 is in phase counting mode. bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 2000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on ?/1024 note: this setting is ignored when channel 2 is in phase counting mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
288 bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 3000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 internal clock: counts on ?/1024 1 0 internal clock: counts on ?/256 1 internal clock: counts on ?/4096 bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 4000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on ?/1024 1 counts on tcnt5 overflow/underflow note: this setting is ignored when channel 4 is in phase counting mode. bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 5000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on ?/256 1 external clock: counts on tclkd pin input note: this setting is ignored when channel 5 is in phase counting mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
289 9.2.2 timer mode register (tmdr) 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : channel 0: tmdr0 channel 3: tmdr3 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : channel 1: tmdr1 channel 2: tmdr2 channel 4: tmdr4 channel 5: tmdr5 the tmdr registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. the tpu has six tmdr registers, one for each channel. the tmdr registers are initialized to h'c0 by a reset, and in hardware standby mode. tmdr register settings should be made only when tcnt operation is stopped. bits 7 and 6reserved: read-only bits, always read as 1. bit 5buffer operation b (bfb): specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
290 bit 5 bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd used together for buffer operation bit 4buffer operation a (bfa): specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. bit 4 bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc used together for buffer operation bits 3 to 0modes 3 to 0 (md3 to md0): these bits are used to set the timer operating mode. bit 3 bit 2 bit 1 bit 0 md3 * 1 md2 * 2 md1 md0 description 0000 normal operation (initial value) 1 reserved 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 *** * : dont care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
291 9.2.3 timer i/o control register (tior) 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : channel 0: tior0h channel 1: tior1 channel 2: tior2 channel 3: tior3h channel 4: tior4 channel 5: tior5 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w channel 0: tior0l channel 3: tior3l note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the re g ister operates as a buffer re g ister. bit initial value r/w : : : the tior registers are 8-bit registers that control the tgr registers. the tpu has eight tior registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. the tior registers are initialized to h'00 by a reset, and in hardware standby mode. care is required since tior is affected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
292 bits 7 to 4 i/o control b3 to b0 (iob3 to iob0) i/o control d3 to d0 (iod3 to iod0): bits iob3 to iob0 specify the function of tgrb. bits iod3 to iod0 specify the function of tgrd. bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 0 000 1 0 1 0 1 tgr0b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0b is input capture register capture input source is tiocb0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 1/count clock input capture at tcnt1 count- up/count-down * 1 * : dont care note: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and ?/1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
293 bit 7 bit 6 bit 5 bit 4 channel iod3 iod2 iod1 iod0 description 0 000 1 0 1 0 1 tgr0d is output compare register * 2 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0d is input capture register * 2 capture input source is tiocd0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * 1 * : dont care notes: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and ?/1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
294 bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 1 000 1 0 1 0 1 tgr1b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 0 0 1 0 1 * tgr1b is input capture register capture input source is tiocb1 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is tgr0c compare match/ input capture input capture at generation of tgr0c compare match/input capture * : dont care bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 2 000 1 0 1 0 1 tgr2b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr2b is input capture register capture input source is tiocb2 pin input capture at rising edge input capture at falling edge input capture at both edges * : dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
295 bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 3 000 1 0 1 0 1 tgr3b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr3b is input capture register capture input source is tiocb3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * 1 * : dont care note: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and ?/1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
296 bit 7 bit 6 bit 5 bit 4 channel iod3 iod2 iod1 iod0 description 3 000 1 0 1 0 1 tgr3d is output compare register * 2 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr3d is input capture register * 2 capture input source is tiocd3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * 1 * : dont care notes: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and ?/1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
297 bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 4 000 1 0 1 0 1 tgr4b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr4b is input capture register capture input source is tiocb4 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is tgr3c compare match/ input capture input capture at generation of tgr3c compare match/ input capture * : dont care bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 5 000 1 0 1 0 1 tgr5b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr5b is input capture register capture input source is tiocb5 pin input capture at rising edge input capture at falling edge input capture at both edges * : dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
298 bits 3 to 0 i/o control a3 to a0 (ioa3 to ioa0) i/o control c3 to c0 (ioc3 to ioc0): ioa3 to ioa0 specify the function of tgra. ioc3 to ioc0 specify the function of tgrc. bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 0 000 1 0 1 0 1 tgr0a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0a is input capture register capture input source is tioca0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 1/ count clock input capture at tcnt1 count-up/count-down * : dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
299 bit 3 bit 2 bit 1 bit 0 channel ioc3 ioc2 ioc1 ioc0 description 0 000 1 0 1 0 1 tgr0c is output compare register * 1 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0c is input capture register * 1 capture input source is tiocc0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * : dont care note: 1. when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
300 bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 1 000 1 0 1 0 1 tgr1a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr1a is input capture register capture input source is tioca1 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is tgr0a compare match/ input capture input capture at generation of channel 0/tgr0a compare match/input capture * : dont care bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 2 000 1 0 1 0 1 tgr2a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr2a is input capture register capture input source is tioca2 pin input capture at rising edge input capture at falling edge input capture at both edges * : dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
301 bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 3 000 1 0 1 0 1 tgr3a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr3a is input capture register capture input source is tioca3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * : dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
302 bit 3 bit 2 bit 1 bit 0 channel ioc3 ioc2 ioc1 ioc0 description 3 000 1 0 1 0 1 tgr3c is output compare register * 1 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr3c is input capture register * 1 capture input source is tiocc3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * : dont care note: 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
303 bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 4 000 1 0 1 0 1 tgr4a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr4a is input capture register capture input source is tioca4 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is tgr3a compare match/ input capture input capture at generation of tgr3a compare match/input capture * : dont care bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 5 000 1 0 1 0 1 tgr5a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr5a is input capture register capture input source is tioca5 pin input capture at rising edge input capture at falling edge input capture at both edges * : dont care www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
304 9.2.4 timer interrupt enable register (tier) 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value r/w : : : channel 0: tier0 channel 3: tier3 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w channel 1: tier1 channel 2: tier2 channel 4: tier4 channel 5: tier5 bit initial value r/w : : : the tier registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. the tpu has six tier registers, one for each channel. the tier registers are initialized to h'40 by a reset, and in hardware standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
305 bit 7a/d conversion start request enable (ttge): enables or disables generation of a/d conversion start requests by tgra input capture/compare match. bit 7 ttge description 0 a/d conversion start request generation disabled (initial value) 1 a/d conversion start request generation enabled bit 6reserved: read-only bit, always read as 1. bit 5underflow interrupt enable (tcieu): enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1 and 2. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcieu description 0 interrupt requests (tciu) by tcfu disabled (initial value) 1 interrupt requests (tciu) by tcfu enabled bit 4overflow interrupt enable (tciev): enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. bit 4 tciev description 0 interrupt requests (tciv) by tcfv disabled (initial value) 1 interrupt requests (tciv) by tcfv enabled bit 3tgr interrupt enable d (tgied): enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgied description 0 interrupt requests (tgid) by tgfd bit disabled (initial value) 1 interrupt requests (tgid) by tgfd bit enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
306 bit 2tgr interrupt enable c (tgiec): enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgiec description 0 interrupt requests (tgic) by tgfc bit disabled (initial value) 1 interrupt requests (tgic) by tgfc bit enabled bit 1tgr interrupt enable b (tgieb): enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. bit 1 tgieb description 0 interrupt requests (tgib) by tgfb bit disabled (initial value) 1 interrupt requests (tgib) by tgfb bit enabled bit 0tgr interrupt enable a (tgiea): enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. bit 0 tgiea description 0 interrupt requests (tgia) by tgfa bit disabled (initial value) 1 interrupt requests (tgia) by tgfa bit enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
307 9.2.5 timer status register (tsr) 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value r/w note: * can only be written with 0 for flag clearing. : : : channel 0: tsr0 channel 3: tsr3 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * channel 1: tsr1 channel 2: tsr2 channel 4: tsr4 channel 5: tsr5 bit initial value r/w note: * can only be written with 0 for flag clearing. : : : the tsr registers are 8-bit registers that indicate the status of each channel. the tpu has six tsr registers, one for each channel. the tsr registers are initialized to h'c0 by a reset, and in hardware standby mode. bit 7count direction flag (tcfd): status flag that shows the direction in which tcnt counts in channels 1, 2, 4, and 5. in channels 0 and 3, bit 7 is reserved. it is always read as 1 and cannot be modified. bit 7 tcfd description 0 tcnt counts down 1 tcnt counts up (initial value) bit 6reserved: read-only bit, always read as 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
308 bit 5underflow flag (tcfu): status flag that indicates that tcnt underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcfu description 0 [clearing condition] (initial value) when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) bit 4overflow flag (tcfv): status flag that indicates that tcnt overflow has occurred. bit 4 tcfv description 0 [clearing condition] (initial value) when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) bit 3input capture/output compare flag d (tgfd): status flag that indicates the occurrence of tgrd input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgfd description 0 [clearing conditions] (initial value) when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfd after reading tgfd = 1 1 [setting conditions] when tcnt = tgrd while tgrd is functioning as output compare register when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register bit 2input capture/output compare flag c (tgfc): status flag that indicates the occurrence of tgrc input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
309 bit 2 tgfc description 0 [clearing conditions] (initial value) when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfc after reading tgfc = 1 1 [setting conditions] when tcnt = tgrc while tgrc is functioning as output compare register when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register bit 1input capture/output compare flag b (tgfb): status flag that indicates the occurrence of tgrb input capture or compare match. bit 1 tgfb description 0 [clearing conditions] (initial value) when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register bit 0input capture/output compare flag a (tgfa): status flag that indicates the occurrence of tgra input capture or compare match. bit 0 tgfa description 0 [clearing conditions] (initial value) when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
310 9.2.6 timer counter (tcnt) 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w channel 0: tcnt0 (up-counter) channel 1: tcnt1 (up/down-counter * ) channel 2: tcnt2 (up/down-counter * ) channel 3: tcnt3 (up-counter) channel 4: tcnt4 (up/down-counter * ) channel 5: tcnt5 (up/down-counter * ) note : * these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. the tcnt registers are 16-bit counters. the tpu has six tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset, and in hardware standby mode. the tcnt counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
311 9.2.7 timer general register (tgr) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w the tgr registers are 16-bit registers with a dual function as output compare and input capture registers. the tpu has 16 tgr registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. tgrc and tgrd for channels 0 and 3 can also be designated for operation as buffer registers*. the tgr registers are initialized to h'ffff by a reset, and in hardware standby mode. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. note: * tgr buffer register combinations are tgra?grc and tgrb?grd. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
312 9.2.8 timer start register (tstr) 7 0 6 0 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w bit initial value r/w : : : tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. tstr is initialized to h'00 by a reset, and in hardware standby mode. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. bits 7 and 6reserved: should always be written with 0. bits 5 to 0counter start 5 to 0 (cst5 to cst0): these bits select operation or stoppage for tcnt. bit n cstn description 0 tcntn count operation is stopped (initial value) 1 tcntn performs count operation n = 5 to 0 note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
313 9.2.9 timer synchro register (tsyr) 7 0 6 0 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w bit initial value r/w : : : tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. tsyr is initialized to h'00 by a reset, and in hardware standby mode. bits 7 and 6reserved: should always be written with 0. bits 5 to 0timer synchro 5 to 0 (sync5 to sync0): these bits select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, synchronous presetting of multiple channels* 1 , and synchronous clearing through counter clearing on another channel* 2 are possible. bit n syncn description 0 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) (initial value) 1 tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible n = 5 to 0 notes: 1. to set synchronous operation, the sync bits for at least two channels must be set to 1. 2. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
314 9.2.10 module stop control register (mstpcr) 15 0 r/w bit initial value r/w : : : 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl mstpcr is a 16-bit readable/writable register that performs module stop mode control. when the mstp13 bit in mstpcr is set to 1, tpu operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 19.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 13module stop (mstp13): specifies the tpu module stop mode. bit 13 mstp13 description 0 tpu module stop mode cleared 1 tpu module stop mode set (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
315 9.3 interface to bus master 9.3.1 16-bit registers tcnt and tgr are 16-bit registers. as the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. an example of 16-bit register access operation is shown in figure 9-2. bus interface h internal data bus l bus master module data bus tcnth tcntl figure 9-2 16-bit register access operation [bus master ? tcnt (16 bits)] 9.3.2 8-bit registers registers other than tcnt and tgr are 8-bit. as the data bus to the cpu is 16 bits wide, these registers can be read and written to in 16-bit units. they can also be read and written to in 8-bit units. examples of 8-bit register access operation are shown in figures 9-3, 9-4, and 9-5. bus interface h internal data bus l module data bus tcr bus master figure 9-3 8-bit register access operation [bus master ? tcr (upper 8 bits)] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
316 bus interface h internal data bus l module data bus tmdr bus master figure 9-4 8-bit register access operation [bus master ? tmdr (lower 8 bits)] bus interface h internal data bus l module data bus tcr tmdr bus master figure 9-5 8-bit register access operation [bus master ? tcr and tmdr (16 bits)] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
317 9.4 operation 9.4.1 overview operation in each mode is outlined below. normal operation: each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. synchronous operation: when synchronous operation is designated for a channel, tcnt for that channel performs synchronous presetting. that is, when tcnt for a channel designated for synchronous operation is rewritten, the tcnt counters for the other channels are also rewritten at the same time. synchronous clearing of the tcnt counters is also possible by setting the timer synchronization bits in tsyr for channels designated for synchronous operation. buffer operation when tgr is an output compare register when a compare match occurs, the value in the buffer register for the relevant channel is transferred to tgr. when tgr is an input capture register when input capture occurs, the value in tcnt is transfer to tgr and the value previously held in tgr is transferred to the buffer register. cascaded operation: the channel 1 counter (tcnt1), channel 2 counter (tcnt2), channel 4 counter (tcnt4), and channel 5 counter (tcnt5) can be connected together to operate as a 32- bit counter. pwm mode: in this mode, a pwm waveform is output. the output level can be set by means of tior. a pwm waveform with a duty of between 0% and 100% can be output, according to the setting of each tgr register. phase counting mode: in this mode, tcnt is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. when phase counting mode is set, the corresponding tclk pin functions as the clock pin, and tcnt performs up- or down-counting. this can be used for two-phase encoder pulse input. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
318 9.4.2 basic functions counter operation: when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counter, periodic counter, and so on. example of count operation setting procedure figure 9-6 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count operation [1] [2] [4] [3] [5] free-running counter start count operation [5] [1] [2] [3] [4] [5] select output compare register select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. for periodic counter operation, select the tgr to be used as the tcnt clearing source with bits cclr2 to cclr0 in tcr. designate the tgr selected in [2] as an output compare register by means of tior. set the periodic counter cycle in the tgr selected in [2]. set the cst bit in tstr to 1 to start the counter operation. figure 9-6 example of counter operation setting procedure www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
319 free-running count operation and periodic count operation immediately after a reset, the tpu?s tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 9-7 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 9-7 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts up-count operation as periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
320 figure 9-8 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software or dtc activation figure 9-8 periodic counter operation waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare match. example of setting procedure for waveform output by compare match figure 9-9 shows an example of the setting procedure for waveform output by compare match select waveform output mode output selection set output timing start count operation [1] [2] [3] [1] select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of tior. the set initial value is output at the tioc pin until the first compare match occurs. [2] set the timing for compare match generation in tgr. [3] set the cst bit in tstr to 1 to start the count operation. figure 9-9 example of setting procedure for waveform output by compare match www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
321 examples of waveform output operation figure 9-10 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made so that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1 output 0 output figure 9-10 example of 0 output/1 output operation figure 9-11 shows an example of toggle output. in this example tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 9-11 example of toggle output operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
322 input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. for channels 0, 1, 3, and 4, it is also possible to specify another channels counter input clock or compare match signal as the input capture source. note: when another channels counter input clock is used as the input capture input for channels 0 and 3, ?/1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if ?/1 is selected. example of input capture operation setting procedure figure 9-12 shows an example of the input capture operation setting procedure. select input capture input input selection start count [1] [2] [1] designate tgr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] set the cst bit in tstr to 1 to start the count operation. figure 9-12 example of input capture operation setting procedure www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
323 example of input capture operation figure 9-13 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 9-13 example of input capture operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
324 9.4.3 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 5 can all be designated for synchronous operation. example of synchronous operation setting procedure: figure 9-14 shows an example of the synchronous operation setting procedure. set synchronous operation synchronous operation selection set tcnt synchronous presetting [1] [2] synchronous clearing select counter clearing source [3] start count [5] set synchronous counter clearing [4] start count [5] clearing sourcegeneration channel? no yes [1] [2] [3] [4] [5] set to 1 the sync bits in tsyr corresponding to the channels to be designated for synchronous operation. when the tcnt counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other tcnt counters. use bits cclr2 to cclr0 in tcr to specify tcnt clearing by input capture/output compare, etc. use bits cclr2 to cclr0 in tcr to designate synchronous clearing for the counter clearing source. set to 1 the cst bits in tstr for the relevant channels, to start the count operation. figure 9-14 example of synchronous operation setting procedure www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
325 example of synchronous operation: figure 9-15 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 0 to 2, tgr0b compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. at this time, synchronous presetting, and synchronous clearing by tgr0b compare match, is performed for channel 0 to 2 tcnt counters, and the data set in tgr0b is used as the pwm cycle. for details of pwm modes, see section 9.4.6, pwm modes. tcnt0 to tcnt2 values h'0000 tioc0a tioc1a time tgr0b synchronous clearing by tgr0b compare match tgr2a tgr1a tgr2b tgr0a tgr1b tioc2a figure 9-15 example of synchronous operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
326 9.4.4 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 9-5 shows the register combinations used in buffer operation. table 9-5 register combinations in buffer operation channel timer general register buffer register 0 tgr0a tgr0c tgr0b tgr0d 3 tgr3a tgr3c tgr3b tgr3d when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 9-16. buffer register timer general register tcnt comparator compare match signal figure 9-16 compare match buffer operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
327 when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 9-17. buffer register timer general register tcnt input capture signal figure 9-17 input capture buffer operation example of buffer operation setting procedure: figure 9-18 shows an example of the buffer operation setting procedure. select tgr function buffer operation set buffer operation start count [1] [2] [3] [1] designate tgr as an input capture register or output compare register by means of tior. [2] designate tgr for buffer operation with bits bfa and bfb in tmdr. [3] set the cst bit in tstr to 1 to start the count operation. figure 9-18 example of buffer operation setting procedure www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
328 examples of buffer operation when tgr is an output compare register figure 9-19 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been set, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time compare match a occurs. for details of pwm modes, see section 9.4.6, pwm modes. tcnt value tgr0b h'0000 tgr0c time tgr0a h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgr0a h'0450 h'0200 transfer figure 9-19 example of buffer operation (1) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
329 when tgr is an input capture register figure 9-20 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 9-20 example of buffer operation (2) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
330 9.4.5 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of tcnt2 (tcnt5) as set in bits tpsc2 to tpsc0 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 9-6 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. table 9-6 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt1 tcnt2 channels 4 and 5 tcnt4 tcnt5 example of cascaded operation setting procedure: figure 9-21 shows an example of the setting procedure for cascaded operation. set cascading cascaded operation start count [1] [2] [1] set bits tpsc2 to tpsc0 in the channel 1 (channel 4) tcr to b?11 to select tcnt2 (tcnt5) overflow/underflow counting. [2] set the cst bit in tstr for the upper and lower channel to 1 to start the count operation. figure 9-21 cascaded operation setting procedure www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
331 examples of cascaded operation: figure 9-22 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, tgr1a and tgr2a have been designated as input capture registers, and tioc pin rising edge has been selected. when a rising edge is input to the tioca1 and tioca2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to tgr1a, and the lower 16 bits to tgr2a. tcnt2 clock tcnt2 h'ffff h'0000 h'0001 tioca1, tioca2 tgr1a h'03a2 tgr2a h'0000 tcnt1 clock tcnt1 h'03a1 h'03a2 figure 9-22 example of cascaded operation (1) figure 9-23 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, and phase counting mode has been designated for channel 2. tcnt1 is incremented by tcnt2 overflow and decremented by tcnt2 underflow. tclka tcnt2 fffd tcnt1 0001 tclkb fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 9-23 example of cascaded operation (2) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
332 9.4.6 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each tgr. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa3 to ioa0 and ioc3 to ioc0 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob3 to iob0 and iod3 to iod0 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in tior. if the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 15-phase pwm output is possible by combined use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 9-7. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
333 table 9-7 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 0 tgr0a tioca0 tioca0 tgr0b tiocb0 tgr0c tiocc0 tiocc0 tgr0d tiocd0 1 tgr1a tioca1 tioca1 tgr1b tiocb1 2 tgr2a tioca2 tioca2 tgr2b tiocb2 3 tgr3a tioca3 tioca3 tgr3b tiocb3 tgr3c tiocc3 tiocc3 tgr3d tiocd3 4 tgr4a tioca4 tioca4 tgr4b tiocb4 5 tgr5a tioca5 tioca5 tgr5b tiocb5 note: in pwm mode 2, pwm output is not possible for the tgr register in which the period is set. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
334 example of pwm mode setting procedure: figure 9-24 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level [1] [2] [3] set tgr [4] set pwm mode [5] start count [6] [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. [2] use bits cclr2 to cclr0 in tcr to select the tgr to be used as the tcnt clearing source. [3] use tior to designate the tgr as an output compare register, and select the initial value and output value. [4] set the cycle in the tgr selected in [2], and set the duty in the other the tgr. [5] select the pwm mode with bits md3 to md0 in tmdr. [6] set the cst bit in tstr to 1 to start the count operation. figure 9-24 example of pwm mode setting procedure examples of pwm mode operation: figure 9-25 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is used as the period, and the values set in tgrb registers as the duty. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
335 tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 9-25 example of pwm mode operation (1) figure 9-26 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgr1b compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgr0a to tgr0d, tgr1a), to output a 5-phase pwm waveform. in this case, the value set in tgr1b is used as the cycle, and the values set in the other tgrs as the duty. tcnt value tgr1b h'0000 tioca0 counter cleared by tgr1b compare match tgr1a tgr0d tgr0c tgr0b tgr0a tiocb0 tiocc0 tiocd0 tioca1 time figure 9-26 example of pwm mode operation (2) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
336 figure 9-27 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0% duty figure 9-27 example of pwm mode operation (3) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
337 9.4.7 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/decremented accordingly. this mode can be set for channels 1, 2, 4, and 5. when phase counting mode is set, an external clock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and input capture/compare match and interrupt functions can be used. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag provides an indication of whether tcnt is counting up or down. table 9-8 shows the correspondence between external clock pins and channels. table 9-8 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 or 5 is set to phase counting mode tclka tclkb when channel 2 or 4 is set to phase counting mode tclkc tclkd example of phase counting mode setting procedure: figure 9-28 shows an example of the phase counting mode setting procedure. select phase counting mode phase counting mode start count [1] [2] [1] select phase counting mode with bits md3 to md0 in tmdr. [2] set the cst bit in tstr to 1 to start the count operation. figure 9-28 example of phase counting mode setting procedure www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
338 examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. phase counting mode 1 figure 9-29 shows an example of phase counting mode 1 operation, and table 9-9 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 9-29 example of phase counting mode 1 operation table 9-9 up/down-count conditions in phase counting mode 1 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level high level high level down-count low level high level low level legend : rising edge : falling edge www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
339 phase counting mode 2 figure 9-30 shows an example of phase counting mode 2 operation, and table 9-10 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 9-30 example of phase counting mode 2 operation table 9-10 up/down-count conditions in phase counting mode 2 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level dont care low level dont care low level dont care high level up-count high level dont care low level dont care high level dont care low level down-count legend : rising edge : falling edge www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
340 phase counting mode 3 figure 9-31 shows an example of phase counting mode 3 operation, and table 9-11 summarizes the tcnt up/down-count conditions. tcnt value time up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) down-count figure 9-31 example of phase counting mode 3 operation table 9-11 up/down-count conditions in phase counting mode 3 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level dont care low level dont care low level dont care high level up-count high level down-count low level dont care high level dont care low level dont care legend : rising edge : falling edge www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
341 phase counting mode 4 figure 9-32 shows an example of phase counting mode 4 operation, and table 9-12 summarizes the tcnt up/down-count conditions. time tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) up-count down-count tcnt value figure 9-32 example of phase counting mode 4 operation table 9-12 up/down-count conditions in phase counting mode 4 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level dont care high level high level down-count low level high level dont care low level legend : rising edge : falling edge www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
342 phase counting mode application example: figure 9-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgr0c compare match; tgr0a and tgr0c are used for the compare match function, and are set with the speed control period and position control period. tgr0b is used for input capture, with tgr0b and tgr0d operating in buffer mode. the channel 1 counter input clock is designated as the tgr0b input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. tgr1a and tgr1b for channel 1 are designated for input capture, channel 0 tgr0a and tgr0c compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. this procedure enables accurate position/speed detection to be achieved. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
343 tcnt1 tcnt0 channel 1 tgr1a (speed period capture) tgr0a (speed control period) tgr1b (position period capture) tgr0c (position control period) tgr0b (pulse width capture) tgr0d (buffer operation) channel 0 tclka tclkb edge detection circuit + + figure 9-33 phase counting mode application example 9.5 interrupts 9.5.1 interrupt sources and priorities there are three kinds of tpu interrupt source: tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by clearing the status flag to 0. relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. for details, see section 5, interrupt controller. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
344 table 9-13 lists the tpu interrupt sources. table 9-13 tpu interrupt sources channel interrupt source description dtc activation priority 0 tgi0a tgr0a input capture/compare match possible high tgi0b tgr0b input capture/compare match possible tgi0c tgr0c input capture/compare match possible tgi0d tgr0d input capture/compare match possible tci0v tcnt0 overflow not possible 1 tgi1a tgr1a input capture/compare match possible tgi1b tgr1b input capture/compare match possible tci1v tcnt1 overflow not possible tci1u tcnt1 underflow not possible 2 tgi2a tgr2a input capture/compare match possible tgi2b tgr2b input capture/compare match possible tci2v tcnt2 overflow not possible tci2u tcnt2 underflow not possible 3 tgi3a tgr3a input capture/compare match possible tgi3b tgr3b input capture/compare match possible tgi3c tgr3c input capture/compare match possible tgi3d tgr3d input capture/compare match possible tci3v tcnt3 overflow not possible 4 tgi4a tgr4a input capture/compare match possible tgi4b tgr4b input capture/compare match possible tci4v tcnt4 overflow not possible tci4u tcnt4 underflow not possible 5 tgi5a tgr5a input capture/compare match possible tgi5b tgr5b input capture/compare match possible tci5v tcnt5 overflow not possible tci5u tcnt5 underflow not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
345 input capture/compare match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt request is cleared by clearing the tgf flag to 0. the tpu has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the tpu has six overflow interrupts, one for each channel. underflow interrupt: an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has four overflow interrupts, one each for channels 1, 2, 4, and 5. 9.5.2 dtc activation dtc activation: the dtc can be activated by the tgr input capture/compare match interrupt for a channel. for details, see section 7, data transfer controller. a total of 16 tpu input capture/compare match interrupts can be used as dtc activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 9.5.3 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match for a channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to start a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. in the tpu, a total of six tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
346 9.6 operation timing 9.6.1 input/output timing tcnt count timing: figure 9-34 shows tcnt count timing in internal clock operation, and figure 9-35 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock n? n n+1 n+2 falling edge rising edge figure 9-34 count timing in internal clock operation tcnt tcnt input clock external clock n? n n+1 n+2 rising edge falling edge falling edge figure 9-35 count timing in external clock operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
347 output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin. after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 9-36 shows output compare output timing. tgr tcnt tcnt input clock n n n+1 compare match signal tioc pin figure 9-36 output compare output timing input capture signal timing: figure 9-37 shows input capture signal timing. tcnt input capture input n n+1 n+2 n n+2 tgr input capture signal figure 9-37 input capture input signal timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
348 timing for counter clearing by compare match/input capture: figure 9-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 9-39 shows the timing when counter clearing by input capture occurrence is specified. tcnt counter clear signal compare match signal tgr n n h'0000 figure 9-38 counter clear timing (compare match) tcnt counter clear signal input capture signal tgr n h'0000 n figure 9-39 counter clear timing (input capture) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
349 buffer operation timing: figures 9-40 and 9-41 show the timing in buffer operation. tgra, tgrb compare match signal tcnt tgrc, tgrd nn n n n+1 figure 9-40 buffer operation timing (compare match) tgra, tgrb tcnt input capture signal tgrc, tgrd n n n n+1 n n n+1 figure 9-41 buffer operation timing (input capture) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
350 9.6.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 9-42 shows the timing for setting of the tgf flag in tsr by compare match occurrence, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n n n+1 compare match signal tgf flag tgi interrupt figure 9-42 tgi interrupt timing (compare match) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
351 tgf flag setting timing in case of input capture: figure 9-43 shows the timing for setting of the tgf flag in tsr by input capture occurrence, and tgi interrupt request signal timing. tgr tcnt input capture signal n n tgf flag tgi interrupt figure 9-43 tgi interrupt timing (input capture) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
352 tcfv flag/tcfu flag setting timing: figure 9-44 shows the timing for setting of the tcfv flag in tsr by overflow occurrence, and tciv interrupt request signal timing. figure 9-45 shows the timing for setting of the tcfu flag in tsr by underflow occurrence, and tciu interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv flag tciv interrupt figure 9-44 tciv interrupt setting timing underflow signal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu flag tciu interrupt figure 9-45 tciu interrupt setting timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
353 status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc is activated, the flag is cleared automatically. figure 9-46 shows the timing for status flag clearing by the cpu, and figure 9-47 shows the timing for status flag clearing by the dtc. status flag write signal address ? tsr address interrupt request signal tsr write cycle t1 t2 figure 9-46 timing for status flag clearing by cpu interrupt request signal status flag address source address dtc read cycle t1 t2 destination address t1 t2 dtc write cycle figure 9-47 timing for status flag clearing by dtc activation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
354 9.7 usage notes note that the kinds of operation and contention described below occur during tpu operation. input clock restrictions: the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. the tpu will not operate properly with a narrower pulse width. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 9-48 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 9-48 phase difference, overlap, and pulse width in phase counting mode caution on period setting: when counter clearing by compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = ? (n + 1) where f : counter frequency ? : operating frequency n : tgr set value www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
355 contention between tcnt write and clear operations: if the counter clear signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 9-49 shows the timing in this case. counter clear signal write signal address tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 9-49 contention between tcnt write and clear operations www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
356 contention between tcnt write and increment operations: if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 9-50 shows the timing in this case. tcnt input clock write signal address tcnt address tcnt tcnt write cycle t1 t2 n m tcnt write data figure 9-50 contention between tcnt write and increment operations www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
357 contention between tgr write and compare match: if a compare match occurs in the t2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is inhibited. a compare match does not occur even if the same value as before is written. figure 9-51 shows the timing in this case. compare match signal write signal address tgr address tcnt tgr write cycle t1 t2 n m tgr write data tgr n n+1 inhibited figure 9-51 contention between tgr write and compare match www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
358 contention between buffer register write and compare match: if a compare match occurs in the t2 state of a tgr write cycle, the data transferred to tgr by the buffer operation will be the data prior to the write. figure 9-52 shows the timing in this case. compare match signal write signal address buffer register address buffer register tgr write cycle t1 t2 n tgr n m buffer register write data figure 9-52 contention between buffer register write and compare match www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
359 contention between tgr read and input capture: if the input capture signal is generated in the t1 state of a tgr read cycle, the data that is read will be the data after input capture transfer. figure 9-53 shows the timing in this case. input capture signal read signal address tgr address tgr tgr read cycle t1 t2 m internal data bus x m figure 9-53 contention between tgr read and input capture www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
360 contention between tgr write and input capture: if the input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 9-54 shows the timing in this case. input capture signal write signal address tcnt tgr write cycle t1 t2 m tgr m tgr address figure 9-54 contention between tgr write and input capture www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
361 contention between buffer register write and input capture: if the input capture signal is generated in the t2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 9-55 shows the timing in this case. input capture signal write signal address ? tcnt buffer register write cycle t1 t2 n tgr n m m buffer register buffer register address figure 9-55 contention between buffer register write and input capture www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
362 contention between overflow/underflow and counter clearing: if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 9-56 shows the operation timing when a tgr compare match is specified as the clearing source, and h'ffff is set in tgr. counter clear signal tcnt input clock ? tcnt tgf disabled tcfv h'ffff h'0000 figure 9-56 contention between overflow and counter clearing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
363 contention between tcnt write and overflow/underflow: if there is an up-count or down- count in the t2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set . figure 9-57 shows the operation timing when there is contention between tcnt write and overflow. write signal address tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv flag figure 9-57 contention between tcnt write and overflow multiplexing of i/o pins: in the h8s/2355 series, the tclka input pin is multiplexed with the tiocc0 i/o pin, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. when an external clock is input, compare match output should not be performed from a multiplexed pin. interrupts and module stop mode: if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or dtc activation source. interrupts should therefore be disabled before entering module stop mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
365 section 10 8-bit timers 10.1 overview the h8s/2355 series includes an 8-bit timer module with two channels (tmr0 and tmr1). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare match events. the 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 10.1.1 features the features of the 8-bit timer module are listed below. selection of four clock sources the counters can be driven by one of three internal clock signals (?/8, ?/64, or ?/8192) or an external clock input (enabling use as an external event counter). selection of three ways to clear the counters the counters can be cleared on compare match a or b, or by an external reset signal. timer output control by a combination of two compare match signals the timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or pwm output. provision for cascading of two channels ? operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1 for the lower 8 bits (16-bit count mode). ? channel 1 can be used to count channel 0 compare matches (compare match count mode). three independent interrupts compare match a and b and overflow interrupts can be requested independently. a/d converter conversion start trigger can be generated channel 0 compare match a signal can be used as an a/d converter conversion start trigger. module stop mode can be set ? as the initial setting, 8-bit timer operation is halted. register access is enabled by exiting module stop mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
366 10.1.2 block diagram figure 10-1 shows a block diagram of the 8-bit timer module. external clock source internal clock sources ?8 ?64 ?8192 clock 1 clock 0 compare match a1 compare match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tmo0 tmri0 internal bus tcora0 comparator a0 comparator b0 tcorb0 tcsr0 tcr0 tcora1 comparator a1 tcnt1 comparator b1 tcorb1 tcsr1 tcr1 tmci0 tmci1 tcnt0 overflow 1 overflow 0 compare match b1 compare match b0 tmo1 tmri1 a/d conversion start request signal clock select control logic clear 0 figure 10-1 block diagram of 8-bit timer www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
367 10.1.3 pin configuration table 10-1 summarizes the input and output pins of the 8-bit timer. table 10-1 input and output pins of 8-bit timer channel name symbol i/o function 0 timer output pin 0 tmo0 output outputs at compare match timer clock input pin 0 tmci0 input inputs external clock for counter timer reset input pin 0 tmri0 input inputs external reset to counter 1 timer output pin 1 tmo1 output outputs at compare match timer clock input pin 1 tmci1 input inputs external clock for counter timer reset input pin 1 tmri1 input inputs external reset to counter 10.1.4 register configuration table 10-2 summarizes the registers of the 8-bit timer module. table 10-2 8-bit timer registers channel name abbreviation r/w initial value address * 1 0 timer control register 0 tcr0 r/w h'00 h'ffb0 timer control/status register 0 tcsr0 r/(w) * 2 h'00 h'ffb2 time constant register a0 tcora0 r/w h'ff h'ffb4 time constant register b0 tcorb0 r/w h'ff h'ffb6 timer counter 0 tcnt0 r/w h'00 h'ffb8 1 timer control register 1 tcr1 r/w h'00 h'ffb1 timer control/status register 1 tcsr1 r/(w) * 2 h'10 h'ffb3 time constant register a1 tcora1 r/w h'ff h'ffb5 time constant register b1 tcorb1 r/w h'ff h'ffb7 timer counter 1 tcnt1 r/w h'00 h'ffb9 all module stop control register mstpcr r/w h'3fff h'ff3c notes: 1. lower 16 bits of the address 2. only 0 can be written to bits 7 to 5, to clear these flags. each pair of registers for channel 0 and channel 1 is a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word transfer instruction. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
368 10.2 register descriptions 10.2.1 timer counters 0 and 1 (tcnt0, tcnt1) 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 tcnt1 bit initial value r/w : : : tcnt0 and tcnt1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. this clock source is selected by clock select bits cks2 to cks0 of tcr. the cpu can read or write to tcnt0 and tcnt1 at all times. tcnt0 and tcnt1 comprise a single 16-bit register, so they can be accessed together by word transfer instruction. tcnt0 and tcnt1 can be cleared by an external reset input or by a compare match signal. which signal is to be used for clearing is selected by clock clear bits cclr1 and cclr0 of tcr. when a timer counter overflows from h'ff to h'00, ovf in tcsr is set to 1. tcnt0 and tcnt1 are each initialized to h'00 by a reset and in hardware standby mode. 10.2.2 time constant registers a0 and a1 (tcora0, tcora1) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 bit initial value r/w : : : tcora0 and tcora1 are 8-bit readable/writable registers. tcora0 and tcora1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. tcora is continually compared with the value in tcnt. when a match is detected, the corresponding cmfa flag of tcsr is set. note, however, that comparison is disabled during the t2 state of a tcor write cycle. the timer output can be freely controlled by these compare match signals and the settings of bits os1 and os0 of tcsr. tcora0 and tcora1 are each initialized to h'ff by a reset and in hardware standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
369 10.2.3 time constant registers b0 and b1 (tcorb0, tcorb1) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 bit initial value r/w : : : tcorb0 and tcorb1 are 8-bit readable/writable registers. tcorb0 and tcorb1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. tcorb is continually compared with the value in tcnt. when a match is detected, the corresponding cmfb flag of tcsr is set. note, however, that comparison is disabled during the t2 state of a tcor write cycle. the timer output can be freely controlled by these compare match signals and the settings of output select bits os3 and os2 of tcsr. tcorb0 and tcorb1 are each initialized to h'ff by a reset and in hardware standby mode. 10.2.4 time control registers 0 and 1 (tcr0, tcr1) 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : tcr0 and tcr1 are 8-bit readable/writable registers that select the clock source and the time at which tcnt is cleared, and enable interrupts. tcr0 and tcr1 are each initialized to h'00 by a reset and in hardware standby mode. for details of this timing, see section 10.3, operation. bit 7compare match interrupt enable b (cmieb): selects whether cmfb interrupt requests (cmib) are enabled or disabled when the cmfb flag of tcsr is set to 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
370 bit 7 cmieb description 0 cmfb interrupt requests (cmib) are disabled (initial value) 1 cmfb interrupt requests (cmib) are enabled bit 6compare match interrupt enable a (cmiea): selects whether cmfa interrupt requests (cmia) are enabled or disabled when the cmfa flag of tcsr is set to 1. bit 6 cmiea description 0 cmfa interrupt requests (cmia) are disabled (initial value) 1 cmfa interrupt requests (cmia) are enabled bit 5timer overflow interrupt enable (ovie): selects whether ovf interrupt requests (ovi) are enabled or disabled when the ovf flag of tcsr is set to 1. bit 5 ovie description 0 ovf interrupt requests (ovi) are disabled (initial value) 1 ovf interrupt requests (ovi) are enabled bits 4 and 3counter clear 1 and 0 (cclr1 and cclr0): these bits select the method by which tcnt is cleared: by compare match a or b, or by an external reset input. bit 4 bit 3 cclr1 cclr0 description 0 0 clear is disabled (initial value) 1 clear by compare match a 1 0 clear by compare match b 1 clear by rising edge of external reset input bits 2 to 0clock select 2 to 0 (cks2 to cks0): these bits select whether the clock input to tcnt is an internal or external clock. three internal clocks can be selected, all divided from the system clock (?): ?/8, ?/64, and ?/8192. the falling edge of the selected internal clock triggers the count. when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
371 some functions differ between channel 0 and channel 1. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 clock input disabled (initial value) 1 internal clock, counted at falling edge of ?/8 1 0 internal clock, counted at falling edge of ?/64 1 internal clock, counted at falling edge of ?/8192 1 0 0 for channel 0: count at tcnt1 overflow signal * for channel 1: count at tcnt0 compare match a * 1 external clock, counted at rising edge 1 0 external clock, counted at falling edge 1 external clock, counted at both rising and falling edges note: * if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare match signal, no incrementing clock is generated. do not use this setting. 10.2.5 timer control/status registers 0 and 1 (tcsr0, tcsr1) 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w only 0 can be written to bits 7 to 5, to clear these flags. bit initial value r/w : : : note: * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value r/w : : : tcsr0 tcsr1 tcsr0 and tcsr1 are 8-bit registers that display compare match and overflow statuses, and control compare match output. tcsr0 is initialized to h'00, and tcsr1 to h'10, by a reset and in hardware standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
372 bit 7compare match flag b (cmfb): status flag indicating whether the values of tcnt and tcorb match. bit 7 cmfb description 0 [clearing conditions] (initial value) cleared by reading cmfb when cmfb = 1, then writing 0 to cmfb when dtc is activated by cmib interrupt while disel bit of mrb in dtc is 0 1 [setting condition] set when tcnt matches tcorb bit 6compare match flag a (cmfa): status flag indicating whether the values of tcnt and tcora match. bit 6 cmfa description 0 [clearing conditions] (initial value) cleared by reading cmfa when cmfa = 1, then writing 0 to cmfa when dtc is activated by cmia interrupt while disel bit of mrb in dtc is 0 1 [setting condition] set when tcnt matches tcora bit 5timer overflow flag (ovf): status flag indicating that tcnt has overflowed (changed from h'ff to h'00). bit 5 ovf description 0 [clearing condition] (initial value) cleared by reading ovf when ovf = 1, then writing 0 to ovf 1 [setting condition] set when tcnt overflows from h'ff to h'00 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
373 bit 4a/d trigger enable (adte) (tcsr0 only): selects enabling or disabling of a/d converter start requests by compare-match a. in tcsr1, this bit is reserved: it is always read as 1 and cannot be modified. bit 4 adte description 0 a/d converter start requests by compare match a are disabled (initial value) 1 a/d converter start requests by compare match a are enabled bits 3 to 0output select 3 to 0 (os3 to os0): these bits specify how the timer output level is to be changed by a compare match of tcor and tcnt. bits os3 and os2 select the effect of compare match b on the output level, bits os1 and os0 select the effect of compare match a on the output level, and both of them can be controlled independently. note, however, that priorities are set such that: toggle output > 1 output > 0 output. if compare matches occur simultaneously, the output changes according to the compare match with the higher priority. timer output is disabled when bits os3 to os0 are all 0. after a reset, the timer output is 0 until the first compare match event occurs. bit 3 bit 2 os3 os2 description 0 0 no change when compare match b occurs (initial value) 1 0 is output when compare match b occurs 1 0 1 is output when compare match b occurs 1 output is inverted when compare match b occurs (toggle output) bit 1 bit 0 os1 os0 description 0 0 no change when compare match a occurs (initial value) 1 0 is output when compare match a occurs 1 0 1 is output when compare match a occurs 1 output is inverted when compare match a occurs (toggle output) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
374 10.2.6 module stop control register (mstpcr) 15 0 r/w bit initial value r/w : : : 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl mstpcr is a 16-bit readable/writable register that performs module stop mode control. when the mstp12 bit in mstpcr is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 19.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 12module stop (mstp12): specifies the 8-bit timer stop mode. bit 12 mstp12 description 0 8-bit timer module stop mode cleared 1 8-bit timer module stop mode set (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
375 10.3 operation 10.3.1 tcnt incrementation timing tcnt is incremented by input clock pulses (either internal or external). internal clock: three different internal clock signals (?/8, ?/64, or ?/8192) divided from the system clock (?) can be selected, by setting bits cks2 to cks0 in tcr. figure 10-2 shows the count timing. internal clock clock input to tcnt tcnt n? n n+1 figure 10-2 count timing for internal clock input external clock: three incrementation methods can be selected by setting bits cks2 to cks0 in tcr: at the rising edge, the falling edge, and both rising and falling edges. note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. the counter will not increment correctly if the pulse width is less than these values. figure 10-3 shows the timing of incrementation at both edges of an external clock signal. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
376 external clock input clock input to tcnt tcnt n? n n+1 figure 10-3 count timing for external clock input 10.3.2 compare match timing setting of compare match flags a and b (cmfa, cmfb): the cmfa and cmfb flags in tcsr are set to 1 by a compare match signal generated when the tcor and tcnt values match. the compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. therefore, when tcor and tcnt match, the compare match signal is not generated until the next incrementation clock input. figure 10-4 shows this timing. tcnt n n+1 tcor n compare match signal cmf figure 10-4 timing of cmf setting www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
377 timer output timing: when compare match a or b occurs, the timer output changes a specified by bits os3 to os0 in tcsr. depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. figure 10-5 shows the timing when the output is set to toggle at compare match a. compare match a signal timer output pin figure 10-5 timing of timer output timing of compare match clear: the timer counter is cleared when compare match a or b occurs, depending on the setting of the cclr1 and cclr0 bits in tcr. figure 10-6 shows the timing of this operation. n h'00 compare match signal tcnt figure 10-6 timing of compare match clear www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
378 10.3.3 timing of external reset on tcnt tcnt is cleared at the rising edge of an external reset input, depending on the settings of the cclr1 and cclr0 bits in tcr. the clear pulse width must be at least 1.5 states. figure 10-7 shows the timing of this operation. clear signal external reset input pin tcnt n h'00 n? figure 10-7 timing of external reset 10.3.4 timing of overflow flag (ovf) setting the ovf in tcsr is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 10-8 shows the timing of this operation. ovf overflow signal tcnt h'ff h'00 figure 10-8 timing of ovf setting www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
379 10.3.5 operation with cascaded connection if bits cks2 to cks0 in either tcr0 or tcr1 are set to b100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). in this case, the timer operates as below. 16-bit counter mode: when bits cks2 to cks0 in tcr0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. setting of compare match flags ? the cmf flag in tcsr0 is set to 1 when a 16-bit compare match event occurs. ? the cmf flag in tcsr1 is set to 1 when a lower 8-bit compare match event occurs. counter clear specification ? if the cclr1 and cclr0 bits in tcr0 have been set for counter clear at compare match, the 16-bit counter (tcnt0 and tcnt1 together) is cleared when a 16-bit compare match event occurs. the 16-bit counter (tcnt0 and tcnt1 together) is cleared even if counter clear by the tmri0 pin has also been set. ? the settings of the cclr1 and cclr0 bits in tcr1 are ignored. the lower 8 bits cannot be cleared independently. pin output ? control of output from the tmo0 pin by bits os3 to os0 in tcsr0 is in accordance with the 16-bit compare match conditions. ? control of output from the tmo1 pin by bits os3 to os0 in tcsr1 is in accordance with the lower 8-bit compare match conditions. compare match counter mode: when bits cks2 to cks0 in tcr1 are b'100, tcnt1 counts compare match as for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clear are in accordance with the settings for each channel. note on usage: if the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for tcnt0 and tcnt1 are not generated and thus the counters will stop operating. software should therefore avoid using both these modes. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
380 10.4 interrupts 10.4.1 interrupt sources and dtc activation there are three 8-bit timer interrupt sources: cmia, cmib, and ovi. their relative priorities are shown in table 10-3. each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in tcr, and independent interrupt requests are sent for each to the interrupt controller. it is also possible to activate the dtc by means of cmia and cmib interrupts. table 10-3 8-bit timer interrupt sources interrupt source description dtc activation priority cmia0 interrupt by cmfa possible high cmib0 interrupt by cmfb possible ovi0 interrupt by ovf not possible cmia1 interrupt by cmfa possible cmib1 interrupt by cmfb possible ovi1 interrupt by ovf not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. 10.4.2 a/d converter activation the a/d converter can be activated only by channel 0 compare match a. if the adte bit in tcsr0 is set to 1 when the cmfa flag is set to 1 by the occurrence of channel 0 compare match a, a request to start a/d conversion is sent to the a/d converter. if the 8-bit timer conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
381 10.5 sample application in the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 10-9. the control bits are set as follows: [1] in tcr, bit cclr1 is cleared to 0 and bit cclr0 is set to 1 so that the timer counter is cleared when its value matches the constant in tcora. [2] in tcsr, bits os3 to os0 are set to b'0110, causing the output to change to 1 at a tcora compare match and to 0 at a tcorb compare match. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 10-9 example of pulse output www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
382 10.6 usage notes application programmers should note that the following kinds of contention can occur in the 8-bit timer. 10.6.1 contention between tcnt write and clear if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. figure 10-10 shows this operation. address tcnt address internal write signal counter clear signal tcnt n h'00 t 1 t 2 tcnt write cycle by cpu figure 10-10 contention between tcnt write and clear www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
383 10.6.2 contention between tcnt write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the counter is not incremented. figure 10-11 shows this operation. address tcnt address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle by cpu counter write data figure 10-11 contention between tcnt write and increment www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
384 10.6.3 contention between tcor write and compare match during the t 2 state of a tcor write cycle, the tcor write has priority and the compare match signal is disabled even if a compare match event occurs. figure 10-12 shows this operation. address tcor address internal write signal tcnt tcor nm t 1 t 2 tcor write cycle by cpu tcor write data n n+1 compare match signal disabled figure 10-12 contention between tcor write and compare match www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
385 10.6.4 contention between compare matches a and b if compare match events a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match a and compare match b, as shown in table 10-4. table 10-4 timer output priorities output setting priority toggle output high 1 output 0 output no change low 10.6.5 switching of internal clocks and tcnt operation tcnt may increment erroneously when the internal clock is switched over. table 10-5 shows the relationship between the timing at which the internal clock is switched (by writing to the cks1 and cks0 bits) and the tcnt operation. when the tcnt clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. if clock switching causes a change from high to low level, as shown in case 3 in table 10-5, a tcnt clock pulse is generated on the assumption that the switchover is a falling edge. this increments tcnt. the erroneous incrementation can also happen when switching between internal and external clocks. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
386 table 10-5 switching of internal clock and tcnt operation no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n+1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n+1 n+2 3 switching from high to low * 3 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n+1 n+2 * 4 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
387 no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 4 switching from high to high clock before switchover clock after switchover tcnt clock tcnt cks bit write n n+1 n+2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated on the assumption that the switchover is a falling edge; tcnt is incremented. 10.6.6 usage note interrupts and module stop mode: if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or dtc activation source. interrupts should therefore be disabled before entering module stop mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
389 section 11 watchdog timer 11.1 overview the h8s/2355 series has a single-channel on-chip watchdog timer (wdt) for monitoring system operation. the wdt outputs an overflow signal ( wdtovf ) if a system crash prevents the cpu from writing to the timer counter, allowing it to overflow. at the same time, the wdt can also generate an internal reset signal for the h8s/2355 series. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. 11.1.1 features wdt features are listed below. switchable between watchdog timer mode and interval timer mode wdtovf output when in watchdog timer mode if the counter overflows, the wdt outputs wdtovf . it is possible to select whether or not the entire h8s/2355 series is reset at the same time. this internal reset can be a power-on reset or a manual reset. interrupt generation when in interval timer mode if the counter overflows, the wdt generates an interval timer interrupt. choice of eight counter clock sources. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
390 11.1.2 block diagram figure 11-1 shows a block diagram of the wdt. overflow interrupt control wovi (interrupt request signal) wdtovf internal reset signal * reset control rstcsr tcnt tscr ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 clock clock select internal clock sources bus interface module bus legend tcsr tcnt rstcsr note: * : timer control/status register : timer counter : reset control/status register internal bus wdt the type of internal reset signal depends on a register setting. either power-on reset or manual reset can be selected. figure 11-1 block diagram of wdt www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
391 11.1.3 pin configuration table 11-1 describes the wdt output pin. table 11-1 wdt pin name symbol i/o function watchdog timer overflow wdtovf output outputs counter overflow signal in watchdog timer mode 11.1.4 register configuration the wdt has three registers, as summarized in table 11-2. these registers control clock selection, wdt mode switching, and the reset signal. table 11-2 wdt registers address * 1 name abbreviation r/w initial value write * 2 read timer control/status register tcsr r/(w) * 3 h'18 h'ffbc h'ffbc timer counter tcnt r/w h'00 h'ffbc h'ffbd reset control/status register rstcsr r/(w) * 3 h'1f h'ffbe h'ffbf notes: 1. lower 16 bits of the address. 2. for details of write operations, see section 11.2.4, notes on register access. 3. only a write of 0 is permitted to bit 7, to clear the flag. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
392 11.2 register descriptions 11.2.1 timer counter (tcnt) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : tcnt is an 8-bit readable/writable* up-counter. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from the internal clock source selected by bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), either the watchdog timer overflow signal ( wdtovf ) or an interval timer interrupt (wovi) is generated, depending on the mode selected by the wt/ it bit in tcsr. tcnt is initialized to h'00 by a reset, in hardware standby mode, or when the tme bit is cleared to 0. it is not initialized in software standby mode. note: * tcnt is write-protected by a password to prevent accidental overwriting. for details see section 11.2.4, notes on register access. 11.2.2 timer control/status register (tcsr) 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : note: * can onl y be written with 0 for fla g clearin g . tcsr is an 8-bit readable/writable* register. its functions include selecting the clock source to be input to tcnt, and the timer mode. tcr is initialized to h'18 by a reset and in hardware standby mode. it is not initialized in software standby mode. note: * tcsr is write-protected by a password to prevent accidental overwriting. for details see section 11.2.4, notes on register access. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
393 bit 7overflow flag (ovf): indicates that tcnt has overflowed from h'ff to h'00, when in interval timer mode. this flag cannot be set during watchdog timer operation. bit 7 ovf description 0 [clearing condition] cleared by reading tcsr when ovf = 1, then writing 0 to ovf (initial value) 1 [setting condition] set when tcnt overflows (changes from h'ff to h'00) in interval timer mode bit 6timer mode select (wt/ it ): selects whether the wdt is used as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request (wovi) when tcnt overflows. if used as a watchdog timer, the wdt generates the wdtovf signal when tcnt overflows. bit 6 wt/ it description 0 interval timer: sends the cpu an interval timer interrupt request (wovi) when tcnt overflows (initial value) 1 watchdog timer: generates the wdtovf signal when tcnt overflows note: * for details of the case where tcnt overflows in watchdog timer mode, see section 11.2.3, reset control/status register (rstcsr). bit 5timer enable (tme): selects whether tcnt runs or is halted. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt counts bits 4 and 3reserved: read-only bits, always read as 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
394 bits 2 to 0: clock select 2 to 0 (cks2 to cks0): these bits select one of eight internal clock sources, obtained by dividing the system clock (?), for input to tcnt. bit 2 bit 1 bit 0 description cks2 cks1 cks0 clock overflow period (when ? = 20 mhz) * 0 0 0 ?/2 (initial value) 25.6 s 1 ?/64 819.2 s 1 0 ?/128 1.6 ms 1 ?/512 6.6 ms 1 0 0 ?/2048 26.2 ms 1 ?/8192 104.9 ms 1 0 ?/32768 419.4 ms 1 ?/131072 1.68 s note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. 11.2.3 reset control/status register (rstcsr) 7 wovf 0 r/(w) * 6 rste 0 r/w 5 rsts 0 r/w 4 1 3 1 0 1 2 1 1 1 note: * can onl y be written with 0 for fla g clearin g . bit initial value r/w : : : rstcsr is an 8-bit readable/writable* register that controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, but not by the wdt internal reset signal caused by overflows. note: * rstcsr is write-protected by a password to prevent accidental overwriting. for details see section 11.2.4, notes on register access. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
395 bit 7watchdog overflow flag (wovf): indicates that tcnt has overflowed (changed from h'ff to h'00) during watchdog timer operation. this bit is not set in interval timer mode. bit 7 wovf description 0 [clearing condition] (initial value) cleared by reading tcsr when wovf = 1, then writing 0 to wovf 1 [setting condition] set when tcnt overflows (changed from h'ff to h'00) during watchdog timer operation bit 6reset enable (rste): specifies whether or not a reset signal is generated in the h8s/2355 series if tcnt overflows during watchdog timer operation. bit 6 rste description 0 reset signal is not generated if tcnt overflows * (initial value) 1 reset signal is generated if tcnt overflows note: * the modules within the h8s/2355 series are not reset, but tcnt and tcsr within the wdt are reset. bit 5reset select (rsts): selects the type of internal reset generated if tcnt overflows during watchdog timer operation. for details of the types of resets, see section 4, exception handling. bit 5 rsts description 0 power-on reset (initial value) 1 manual reset bits 4 to 0reserved: read-only bits, always read as 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
396 11.2.4 notes on register access the watchdog timers tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr: these registers must be written to by a word transfer instruction. they cannot be written to with byte instructions. figure 11-2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. for a write to tcnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to tcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to tcnt or tcsr. tcnt write tcsr write address: h'ffbc address: h'ffbc h'5a write data 15 8 7 0 h'a5 write data 15 8 7 0 figure 11-2 format of data written to tcnt and tcsr www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
397 writing to rstcsr: rstcsr must be written to by word transfer instruction to address h'ffbe. it cannot be written to with byte instructions. figure 11-3 shows the format of data written to rstcsr. the method of writing 0 to the wovf bit differs from that for writing to the rste and rsts bits. to write 0 to the wovf bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. this clears the wovf bit to 0, but has no effect on the rste and rsts bits. to write to the rste and rsts bits, the upper byte must contain h'5a and the lower byte must contain the write data. this writes the values in bits 6 and 5 of the lower byte into the rste and rsts bits, but has no effect on the wovf bit. h'a5 h'00 15 8 7 0 h'5a write data 15 8 7 0 writing 0 to wovf bit writing to rste and rsts bits address: h'ffbe address: h'ffbe figure 11-3 format of data written to rstcsr reading tcnt, tcsr, and rstcsr: these registers are read in the same way as other registers. the read addresses are h'ffbc for tcsr, h'ffbd for tcnt, and h'ffbf for rstcsr. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
398 11.3 operation 11.3.1 watchdog timer operation to use the wdt as a watchdog timer, set the wt/ it and tme bits to 1. software must prevent tcnt overflows by rewriting the tcnt value (normally be writing h'00) before overflows occurs. this ensures that tcnt does not overflow while the system is operating normally. if tcnt overflows without being rewritten because of a system crash or other error, the wdtovf signal is output. this is shown in figure 11-4. this wdtovf signal can be used to reset the system. the wdtovf signal is output for 132 states when rste = 1, and for 130 states when rste = 0. if tcnt overflows when 1 is set in the rste bit in rstcsr, a signal that resets the h8s/2355 series internally is generated at the same time as the wdtovf signal. this reset can be selected as a power-on reset or a manual reset, depending on the setting of the rsts bit in rstcsr. the internal reset signal is output for 518 states. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. tcnt count h'00 time h'ff wt/it=1 tme=1 h'00 written to tcnt wt/it=1 tme=1 h'00 written to tcnt 132 states * 2 518 states wdtovf signal internal reset signal * 1 wt/it tme notes: 1. the internal reset signal is generated only if the rste bit is set to 1. 2. 130 states when the rste bit is cleared to 0. overflow wdtovf and internal reset are generated wovf=1 : timer mode select bit : timer enable bit legend figure 11-4 watchdog timer operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
399 11.3.2 interval timer operation to use the wdt as an interval timer, clear the wt/ it bit in tcsr to 0 and set the tme bit to 1. an interval timer interrupt (wovi) is generated each time tcnt overflows, provided that the wdt is operating as an interval timer, as shown in figure 11-5. this function can be used to generate interrupt requests at regular intervals. tcnt count h'00 time h'ff wt/ it =0 tme=1 wovi overflow overflow overflow overflow legend wovi: interval timer interrupt re q uest g eneration wovi wovi wovi figure 11-5 interval timer operation 11.3.3 timing of setting overflow flag (ovf) the ovf flag is set to 1 if tcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure 11-6. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
400 ? tcnt h'ff h'00 overflow signal (internal signal) ovf figure 11-6 timing of setting of ovf 11.3.4 timing of setting of watchdog timer overflow flag (wovf) the wovf flag is set to 1 if tcnt overflows during watchdog timer operation. at the same time, the wdtovf signal goes low. if tcnt overflows while the rste bit in rstcsr is set to 1, an internal reset signal is generated for the entire h8s/2355 series chip. figure 11-7 shows the timing in this case. ? tcnt h'ff h'00 overflow signal (internal signal) wovf wdtovf signal internal reset signal 132 states 518 states figure 11-7 timing of setting of wovf www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
401 11.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. 11.5 usage notes 11.5.1 contention between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 11-8 shows this operation. address ? internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 11-8 contention between tcnt write and increment 11.5.2 changing value of cks2 to cks0 if bits cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits cks2 to cks0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
402 11.5.3 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, or vice versa, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. 11.5.4 system reset by wdtovf signal if the wdtovf output signal is input to the res pin of the h8s/2355 series, the h8s/2355 series will not be initialized correctly. make sure that the wdtovf signal is not input logically to the res pin. to reset the entire system by means of the wdtovf signal, use the circuit shown in figure 11-9. reset input reset signal to entire system h8s/2355 res wdtovf figure 11-9 circuit for system reset by wdtovf signal (example) 11.5.5 internal reset in watchdog timer mode the h8s/2355 series is not reset internally if tcnt overflows while the rste bit is cleared to 0 during watchdog timer operation, but tcnt and tscr of the wdt are reset. tcnt, tcsr, and rstcr cannot be written to while the wdtovf signal is low. also note that a read of the wovf flag is not recognized during this period. to clear the wovf falg, therefore, read tcsr after the wdtovf signal goes high, then write 0 to the wovf flag. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
403 section 12 serial communication interface (sci) 12.1 overview the h8s/2355 series is equipped with a 3-channel serial communication interface (sci). all three channels have the same functions. the sci can handle both asynchronous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). 12.1.1 features sci features are listed below. choice of asynchronous or clocked synchronous serial communication mode asynchronous mode ? serial data communication executed using asynchronous system in which synchronization is achieved character by character ? serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia) ? a multiprocessor communication function is provided that enables serial data communication with a number of processors ? choice of 12 serial data transfer formats data length : 7 or 8 bits stop bit length : 1 or 2 bits parity : even, odd, or none multiprocessor bit : 1 or 0 ? receive error detection : parity, overrun, and framing errors ? break detection : break can be detected by reading the rxd pin level directly in case of a framing error clocked synchronous mode ? serial data communication synchronized with a clock serial data communication can be carried out with other chips that have a synchronous communication function ? one serial data transfer format data length : 8 bits ? receive error detection : overrun errors detected www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
404 full-duplex communication capability ? the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ? double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data on-chip baud rate generator allows any bit rate to be selected choice of serial clock source: internal clock from baud rate generator or external clock from sck pin four interrupt sources ? four interrupt sources ? transmit-data-empty, transmit-end, receive-data-full, and receive error ? that can issue requests independently ? the transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (dtc) to execute data transfer choice of lsb-first or msb-first transfer ? can be selected regardless of the communication mode* (except in the case of asynchronous mode bit data) module stop mode can be set ? as the initial setting, sci operation is halted. register access is enabled by exiting module stop mode. note: * descriptions in this section refer to lsb-first transfer. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
405 12.1.2 block diagram figure 12-1 shows a block diagram of the sci. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock ? ?/4 ?/16 ?/64 txi tei rxi eri smr legend scmr rsr rdr tsr tdr smr scr ssr brr : smart card mode register : receive shift register : receive data register : transmit shift register : transmit data register : serial mode register : serial control register : serial status register : bit rate register figure 12-1 block diagram of sci www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
406 12.1.3 pin configuration table 12-1 shows the serial pins for each sci channel. table 12-1 sci pins channel pin name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
407 12.1.4 register configuration the sci has the internal registers shown in table 12-2. these registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. table 12-2 sci registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e 1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 2 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e all module stop control register mstpcr r/w h'3fff h'ff3c notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
408 12.2 register descriptions 12.2.1 receive shift register (rsr) 7 6 5 4 3 0 2 1 bit r/w : : rsr is a register used to receive serial data. the sci sets serial data input from the rxd pin in rsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly read or written to by the cpu. 12.2.2 receive data register (rdr) 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : rdr is a register that stores received serial data. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr where it is stored, and completes the receive operation. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this way, enables continuous receive operations to be performed. rdr is a read-only register, and cannot be written to by the cpu. rdr is initialized to h'00 by a reset, and in standby mode or module stop mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
409 12.2.3 transmit shift register (tsr) 7 6 5 4 3 0 2 1 bit r/w : : tsr is a register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from tdr to tsr, and transmission started, automatically. however, data transfer from tdr to tsr is not performed if the tdre bit in ssr is set to 1. tsr cannot be directly read or written to by the cpu. 12.2.4 transmit data register (tdr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : tdr is an 8-bit register that stores data for serial transmission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts serial transmission. continuous serial transmission can be carried out by writing the next transmit data to tdr during serial transmission of the data in tsr. tdr can be read or written to by the cpu at all times. tdr is initialized to h'ff by a reset, and in standby mode or module stop mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
410 12.2.5 serial mode register (smr) 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : smr is an 8-bit register used to set the sci?s serial transfer format and select the baud rate generator clock source. smr can be read or written to by the cpu at all times. smr is initialized to h'00 by a reset, and in standby mode or module stop mode. bit 7communication mode (c/ a ): selects asynchronous mode or clocked synchronous mode as the sci operating mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 clocked synchronous mode bit 6character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in clocked synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and it is not possible to choose between lsb-first or msb-first transfer. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
411 bit 5parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5 pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is invalid in clocked synchronous mode, and when parity addition and checking is disabled in asynchronous mode. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
412 bit 3stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bits setting is only valid in asynchronous mode. if clocked synchronous mode is set the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit: in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (initial value) 1 2 stop bits: in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. for details of the multiprocessor communication function, see section 12.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
413 bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock source for the baud rate generator. the clock source can be selected from ?, ?/4, ?/16, and ?/64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 12.2.8, bit rate register. bit 1 bit 0 cks1 cks0 description 0 0 ? clock (initial value) 1 ?/4 clock 1 0 ?/16 clock 1 ?/64 clock 12.2.6 serial control register (scr) 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : scr is a register that performs enabling or disabling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scr can be read or written to by the cpu at all times. scr is initialized to h'00 by a reset, and in standby mode or module stop mode. bit 7transmit interrupt enable (tie): enables or disables transmit data empty interrupt (txi) request generation when serial transmit data is transferred from tdr to tsr and the tdre flag in ssr is set to 1. bit 7 tie description 0 transmit data empty interrupt (txi) requests disabled * (initial value) 1 transmit data empty interrupt (txi) requests enabled note: * txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
414 bit 6receive interrupt enable (rie): enables or disables receive data full interrupt (rxi) request and receive error interrupt (eri) request generation when serial receive data is transferred from rsr to rdr and the rdrf flag in ssr is set to 1. bit 6 rie description 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled * (initial value) 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. bit 5transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5 te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in ssr is fixed at 1. 2. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. bit 4receive enable (re): enables or disables the start of serial reception by the sci. bit 4 re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the transfer format before setting the re bit to 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
415 bit 3multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when the mp bit in smr is set to 1. the mpie bit setting is invalid in clocked synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] when the mpie bit is cleared to 0 when mpb= 1 data is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. bit 2transmit end interrupt enable (teie): enables or disables transmit end interrupt (tei) request generation when there is no valid transmit data in tdr in msb data transmission. bit 2 teie description 0 transmit end interrupt (tei) request disabled * (initial value) 1 transmit end interrupt (tei) request enabled * note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
416 bits 1 and 0clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as an i/o port, the serial clock output pin, or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (cke1 = 1). note that the scis operating mode must be decided using smr before setting the cke1 and cke0 bits. for details of clock source selection, see table 12.9 in section 12.3, operation. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock/sck pin functions as i/o port * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output 1 asynchronous mode internal clock/sck pin functions as clock output * 2 clocked synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input * 3 clocked synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input * 3 clocked synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
417 12.2.7 serial status register (ssr) 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : note: only 0 can be written, to clear the flag. ssr is an 8-bit register containing status flags that indicate the operating status of the sci, and multiprocessor bits. ssr can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. ssr is initialized to h'84 by a reset, and in standby mode or module stop mode. bit 7transmit data register empty (tdre): indicates that data has been transferred from tdr to tsr and the next serial data can be written to tdr. bit 7 tdre description 0 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr bit 6receive data register full (rdrf): indicates that the received data is stored in rdr. bit 6 rdrf description 0 [clearing conditions] (initial value) when 0 is written to rdrf after reading rdrf = 1 when the dtc is activated by an rxi interrupt and reads data from rdr 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
418 bit 5overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5 orer description 0 [clearing condition] (initial value) * 1 when 0 is written to orer after reading orer = 1 1 [setting condition] when the next serial reception is completed while rdrf = 1 notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit 4framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4 fer description 0 [clearing condition] (initial value) * 1 when 0 is written to fer after reading fer = 1 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
419 bit 3parity error (per): indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. bit 3 per description 0 [clearing condition] (initial value) * 1 when 0 is written to per after reading per = 1 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 2 notes: 1. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit 2transmit end (tend): indicates that there is no valid data in tdr when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified. bit 2 tend description 0 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1multiprocessor bit (mpb): when reception is performed using multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. mpb is a read-only bit, and cannot be modified. bit 1 mpb description 0 [clearing condition] (initial value) * when data with a 0 multiprocessor bit is received 1 [setting condition] when data with a 1 multiprocessor bit is received note: * retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
420 bit 0multiprocessor bit transfer (mpbt): when transmission is performed using multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. bit 0 mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted 12.2.8 bit rate register (brr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : brr is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in smr. brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset, and in standby mode or module stop mode. as baud rate generator control is performed independently for each channel, different values can be set for each channel. table 12-3 shows sample brr settings in asynchronous mode, and table 12-4 shows sample brr settings in clocked synchronous mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
421 table 12-3 brr settings for various bit rates (asynchronous mode) ? = 2 mhz ? = 2.097152 mhz ? = 2.4576 mhz ? = 3 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 C0.04 1 174 C0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 C0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 C2.48 0 15 0.00 0 19 C2.34 9600 0 6 0 6 C2.48 0 7 0.00 0 9 C2.34 19200 0 2 0 2 0 3 0.00 0 4 C2.34 31250 0 1 0.00 0 1 0 1 0 2 0.00 38400 0 1 0 1 0 1 0.00 ? = 3.6864 mhz ? = 4 mhz ? = 4.9152 mhz ? = 5 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 C0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 C1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 C1.70 0 4 0.00 38400 0 2 0.00 0 2 0 3 0.00 0 3 1.73 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
422 ? = 6 mhz ? = 6.144 mhz ? = 7.3728 mhz ? = 8 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 C0.44 2 108 0.08 2 130 C0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 C2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 C2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 C2.34 0 4 0.00 0 5 0.00 0 6 ? = 9.8304 mhz ? = 10 mhz ? = 12 mhz ? = 12.288 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 C0.26 2 177 C0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 C1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 C2.34 0 19 0.00 31250 0 9 C1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 C2.34 0 9 0.00 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
423 ? = 14 mhz ? = 14.7456 mhz ? = 16 mhz ? = 17.2032 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 C0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 C0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 C0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 C1.70 0 15 0.00 0 16 1.20 38400 0 10 0 11 0.00 0 12 0.16 0 13 0.00 ? = 18 mhz ? = 19.6608 mhz ? = 20 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 3 79 C0.12 3 86 0.31 3 88 C0.25 150 2 233 0.16 2 255 0.00 3 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 C0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 C1.36 31250 0 17 0.00 0 19 C1.70 0 19 0.00 38400 0 14 C2.34 0 15 0.00 0 15 1.73 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
424 table 12-4 brr settings for various bit rates (clocked synchronous mode) bit rate ? = 2 mhz ? = 4 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz (bit/s) n n n n n n n n n n n n 110 3 70 250 2 124 2 249 3 124 3 249 500 1 249 2 124 2 249 3 124 1 k 1 124 1 249 2 124 2 249 2.5 k 0 199 1 99 1 199 1 249 2 99 2 124 5 k 0 99 0 199 1 99 1 124 1 199 1 249 10 k 0 49 0 99 0 199 0 249 1 99 1 124 25 k 0 19 0 39 0 79 0 99 0 159 0 199 50 k 09019039049079099 100 k 0409019024039049 250 k 01030709015019 500 k 0 0 * 0103040709 1 m 0 0 * 010304 2.5 m 0 0 * 0 1 5 m 0 0 * note: as far as possible, the setting should be made so that the error is no more than 1%. legend blank : cannot be set. : can be set, but there will be a degree of error. * : continuous transfer is not possible. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
425 the brr setting is found from the following formulas. asynchronous mode: n = ? 64 2 2ne1 b 10 6 e 1 clocked synchronous mode: n = ? 8 2 2ne1 b 10 6 e 1 where b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) ?: operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) smr setting n clock cks1 cks0 0? 0 0 1 ?/4 0 1 2 ?/16 1 0 3 ?/64 1 1 the bit rate error in asynchronous mode is found from the following formula: error (%) = { ? 10 6 (n + 1) b 64 2 2ne1 e 1 } 100 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
426 table 12-5 shows the maximum bit rate for each frequency in asynchronous mode. tables 12-6 and 12-7 show the maximum bit rates with external clock input. table 12-5 maximum bit rate for each frequency (asynchronous mode) ? (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
427 table 12-6 maximum bit rate with external clock input (asynchronous mode) ? (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
428 table 12-7 maximum bit rate with external clock input (clocked synchronous mode) ? (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
429 12.2.9 smart card mode register (scmr) 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : scmr selects lsb-first or msb-first by means of bit sdir. except in the case of asynchronous mode 7-bit data, lsb-first or msb-first can be selected regardless of the serial communication mode. the descriptions in this chapter refer to lsb-first transfer. for details of the other bits in scmr, see 13.2.1, smart card mode register (scmr). scmr is initialized to h'f2 by a reset, and in standby mode or module stop mode. bits 7 to 4reserved: read-only bits, always read as 1. bit 3smart card data transfer direction (sdir): selects the serial/parallel conversion format. this bit is valid when 8-bit data is used as the transmit/receive format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first bit 2smart card data invert (sinv): when the smart card interface operates as a normal sci, 0 should be written in this bit. bit 1reserved: read-only bit, always read as 1. bit 0smart card interface mode select (smif): when the smart card interface operates as a normal sci, 0 should be written in this bit. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
430 12.2.10 module stop control register (mstpcr) 15 0 r/w bit initial value r/w : : : 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl mstpcr is a 16-bit readable/writable register that performs module stop mode control. when the corresponding bit of bits mstp7 to mstp5 is set to 1, sci operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 19.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7module stop (mstp7): specifies the sci channel 2 module stop mode. bit 7 mstp7 description 0 sci channel 2 module stop mode cleared 1 sci channel 2 module stop mode set (initial value) bit 6module stop (mstp6): specifies the sci channel 1 module stop mode. bit 6 mstp6 description 0 sci channel 1 module stop mode cleared 1 sci channel 1 module stop mode set (initial value) bit 5module stop (mstp5): specifies the sci channel 0 module stop mode. bit 5 mstp5 description 0 sci channel 0 module stop mode cleared 1 sci channel 0 module stop mode set (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
431 12.3 operation 12.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or clocked synchronous mode and the transmission format is made using smr as shown in table 12-8. the sci clock is determined by a combination of the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 12-9. asynchronous mode data length: choice of 7 or 8 bits choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) detection of framing, parity, and overrun errors, and breaks, during reception choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) clocked synchronous mode transfer format: fixed 8-bit data detection of overrun errors during reception choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip ? when external clock is selected: the on-chip baud rate generator is not used, and the sci operates on the input serial clock www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
432 table 12-8 smr settings and serial transfer format selection smr settings sci transfer format bit 7 bit 6 bit 2 bit 5 bit 3 data parity stop bit c/ a chr mp pe stop mode length bit length 00000 asynchronous 8-bit data no no 1 bit 1 mode 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 0 1 0 8-bit data yes no 1 bit 1 2 bits 1 0 7-bit data 1 bit 1 2 bits 1 clocked synchronous mode 8-bit data no none table 12-9 smr and scr settings and sci clock source selection smr scr setting sci transmit/receive clock bit 7 bit 1 bit 0 clock c/ a cke1 cke0 mode source sck pin function 0 0 0 asynchronous internal sci does not use sck pin 1 mode outputs clock with same frequency as bit rate 1 0 external inputs clock with frequency of 16 times 1 the bit rate 1 0 0 internal outputs serial clock 1 1 0 external inputs serial clock 1 multi processor bit asynchronous mode (multi- processor format) clocked synchronous mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
433 12.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by-character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 12-2 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 12-2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
434 data transfer format: table 12-10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. table 12-10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend s : start bit stop : stop bit p : parity bit mpb : multiprocessor bit www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
435 clock: either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the scis serial clock, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 12-9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12-3. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 figure 12-3 relation between output clock and transfer data phase (asynchronous mode) data transfer operations: sci initialization (asynchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
436 figure 12-4 shows a sample sci initialization flowchart. wait start initialization set data transfer format in smr and scmr [1] set cke1 and cke0 bits in scr (te, re bits 0) no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock is selected in asynchronous mode, it is output immediately after scr settings are made. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. figure 12-4 sample sci initialization flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
437 serial data transmission (asynchronous mode) figure 12-5 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre=1 all data transmitted? tend= 1 break output? [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request, and date is written to tdr. [4] break output at the end of serial transmission: to output a break in serial transmission, set ddr for the port corresponding to the txd pin to 1, clear dr to 0, then clear the te bit in scr to 0. figure 12-5 sample serial transmission flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
438 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. a format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
439 figure 12-6 shows an example of the operation for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 12-6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
440 serial data reception (asynchronous mode) figure 12-7 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 read orer, per, and fer flags in ssr error processing (continued on next page) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes per fer orer= 1 rdrf= 1 all data received? sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error processing and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. sci status check and receive data read : read ssr and check that rdrf = 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr, and clear the rdrf flag to 0. the rdrf flag is cleared automatically when the dtc is activated by an rxi interrupt and the rdr value is read. [1] [2] [3] [4] [5] figure 12-7 sample serial reception data flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
441 [3] error processing parity error processing no yes clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing orer= 1 fer= 1 break? per= 1 clear re bit in scr to 0 figure 12-7 sample serial reception data flowchart (cont) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
442 in serial reception, the sci operates as described below. [1] the sci monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] the received data is stored in rsr in lsb-to-msb order. [3] the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. [a] parity check: the sci checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the o/ e bit in smr. [b] stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. [c] status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from rsr to rdr. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error* is detected in the error check, the operation is as shown in table 12-11. note: * subsequent receive operations cannot be performed when a receive error has occurred. also note that the rdrf flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer, per, or fer flag changes to 1, a receive error interrupt (eri) request is generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
443 table 12-11 receive errors and conditions for occurrence receive error abbreviation occurrence condition data transfer overrun error orer when the next data reception is completed while the rdrf flag in ssr is set to 1 receive data is not transferred from rsr to rdr. framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr. parity error per when the received data differs from the parity (even or odd) set in smr receive data is transferred from rsr to rdr. figure 12-8 shows an example of the operation for reception in asynchronous mode. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit rxi interrupt request generated eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine figure 12-8 example of sci operation in reception (example with 8-bit data, parity, one stop bit) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
444 12.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing transmission lines. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station , and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. figure 12-9 shows an example of inter-processor communication using the multiprocessor format. data transfer format: there are four data transfer formats. when the multiprocessor format is specified, the parity bit specification is invalid. for details, see table 12-10. clock: see the section on asynchronous mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
445 transmitting station receiving station a (id= 01) receiving station b (id= 02) receiving station c (id= 03) receiving station d (id= 04) serial transmission line serial data id transmission cycle= receiving station specification data transmission cycle= data transmission to receiving station specified by id (mpb= 1) (mpb= 0) h'01 h'aa legend mpb: multiprocessor bit figure 12-9 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) data transfer operations: multiprocessor serial data transmission figure 12-10 shows a sample flowchart for multiprocessor serial data transmission. the following procedure should be used for multiprocessor serial data transmission. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
446 no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and set mpbt bit in ssr no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre= 1 all data transmitted? tend= 1 break output? clear tdre flag to 0 sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. set the mpbt bit in ssr to 0 or 1. finally, clear the tdre flag to 0. serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request, and data is written to tdr. break output at the end of serial transmission: to output a break in serial transmission, set the port ddr to 1, clear dr to 0, then clear the te bit in scr to 0. [1] [2] [3] [4] figure 12-10 sample multiprocessor serial transmission flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
447 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] multiprocessor bit one multiprocessor bit (mpbt value) is output. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a transmission end interrupt (tei) request is generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
448 figure 12-11 shows an example of sci operation for transmission using the multiprocessor format. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit multi- proce- ssor bit stop bit start bit data multi- proces- sor bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 12-11 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit) multiprocessor serial data reception figure 12-12 shows a sample flowchart for multiprocessor serial reception. the following procedure should be used for multiprocessor serial data reception. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
449 yes [1] no initialization start reception no yes [4] clear re bit in scr to 0 error processing (continued on next page) [5] no yes fer orer= 1 rdrf= 1 all data received? read mpie bit in scr [2] read orer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes this station's id? read orer and fer flags in ssr yes no read rdrf flag in ssr no yes fer orer= 1 read receive data in rdr rdrf= 1 sci initialization: the rxd pin is automatically designated as the receive data input pin. id reception cycle: set the mpie bit in scr to 1. sci status check, id reception and comparison: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station?s id. if the data is not this station?s id, set the mpie bit to 1 again, and clear the rdrf flag to 0. if the data is this station?s id, clear the rdrf flag to 0. sci status check and data reception: read ssr and check that the rdrf flag is set to 1, then read the data in rdr. receive error processing and break detection: if a receive error occurs, read the orer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. [1] [2] [3] [4] [5] figure 12-12 sample multiprocessor serial reception flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
450 error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing orer= 1 fer= 1 break? clear re bit in scr to 0 [5] figure 12-12 sample multiprocessor serial reception flowchart (cont) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
451 figure 12-13 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine if not this stations id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match stations id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id2) start bit mpb stop bit start bit data (data2) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine matches this stations id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 again id2 (b) data matches stations id data2 id1 figure 12-13 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
452 12.3.4 operation in clocked synchronous mode in clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 12-14 shows the general format for clocked synchronous serial communication. dont care dont care one unit of transfer data (character or frame) bit 0 serial data serial clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * note: * high except in continuous transfer * figure 12-14 data format in synchronous communication in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data confirmation is guaranteed at the rising edge of the serial clock. in clocked serial communication, one character consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in clocked synchronous mode, the sci receives data in synchronization with the rising edge of the serial clock. data transfer format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck pin can be selected, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 12-9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
453 eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. when only receive operations are performed, however, the serial clock is output until an overrun error occurs or the re bit is cleared to 0. if you want to perform receive operations in units of one character, you should select an external clock as the clock source. data transfer operations: sci initialization (clocked synchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. figure 12-15 shows a sample sci initialization flowchart. wait note: in simultaneous transmit and receive operations, the te and re bits should both be cleared to 0 or set to 1 simultaneously. start initialization set data transfer format in smr and scmr no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, te and re, to 0. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. set cke1 and cke0 bits in scr (te, re bits 0) figure 12-15 sample sci initialization flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
454 serial data transmission (clocked synchronous mode) figure 12-16 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] clear te bit in scr to 0 tdre= 1 all data transmitted? tend= 1 [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request and data is written to tdr. figure 12-16 sample serial transmission flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
455 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). [3] the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. [4] after completion of serial transmission, the sck pin is fixed. figure 12-17 shows an example of sci operation in transmission. transfer direction bit 7 serial data serial clock 1 frame tdre tend bit 0 bit 7 bit 0 bit 1 bit 7 bit 6 data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated txi interrupt request generated txi interrupt request generated figure 12-17 example of sci operation in transmission www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
456 serial data reception (clocked synchronous mode) figure 12-18 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. when changing the operating mode from asynchronous to clocked synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
457 yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 error processing (continued below) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer= 1 rdrf= 1 all data received? read orer flag in ssr [1] [2] [3] [4] [5] sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error processing: if a receive error occurs, read the orer flag in ssr , and after performing the appropriate error processing, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. the rdrf flag is cleared automatically when the dtc is activated by a receive data full interrupt (rxi) request and the rdr value is read. error processing overrun error processing [3] clear orer flag in ssr to 0 figure 12-18 sample serial reception flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
458 in serial reception, the sci operates as described below. [1] the sci performs internal initialization in synchronization with serial clock input or output. [2] the received data is stored in rsr in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0 and the receive data can be transferred from rsr to rdr. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error is detected in the error check, the operation is as shown in table 12-11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer flag changes to 1, a receive error interrupt (eri) request is generated. figure 12-19 shows an example of sci operation in reception. bit 7 serial data serial clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine rxi interrupt request generated eri interrupt request generated by overrun error figure 12-19 example of sci operation in reception simultaneous serial data transmission and reception (clocked synchronous mode) figure 12-20 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
459 yes [1] no initialization start transmission/reception [5] error processing [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer= 1 all data received? [2] read tdre flag in ssr no yes tdre= 1 write transmit data to tdr and clear tdre flag in ssr to 0 no yes rdrf= 1 read orer flag in ssr [4] read rdrf flag in ssr clear te and re bits in scr to 0 note: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 simultaneously. [1] [2] [3] [4] [5] sci initialization: the txd pin is designated as the transmit data output pin, and the rxd pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. receive error processing: if a receive error occurs, read the orer flag in ssr , and after performing the appropriate error processing, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial transmission/reception continuation procedure: to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr and clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request and data is written to tdr. also, the rdrf flag is cleared automatically when the dtc is activated by a receive data full interrupt (rxi) request and the rdr value is read. figure 12-20 sample flowchart of simultaneous serial transmit and receive operations www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
460 12.4 sci interrupts the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full interrupt (rxi) request, and transmit-data-empty interrupt (txi) request. table 12-12 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in the scr. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dtc to perform data transfer. the tdre flag is cleared to 0 automatically when data transfer is performed by the dtc. the dtc cannot be activated by a tei interrupt request. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt can activate the dtc to perform data transfer. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dtc. the dtc cannot be activated by an eri interrupt request. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
461 table 12-12 sci interrupt sources channel interrupt source description dtc activation priority * 0 eri interrupt due to receive error (orer, fer, or per) not possible high rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible 1 eri interrupt due to receive error (orer, fer, or per) not possible rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible 2 eri interrupt due to receive error (orer, fer, or per) not possible rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible low note: * this table shows the initial state immediately after a reset. relative priorities among channels can be changed by means of the interrupt controller. a tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. the tend flag is cleared at the same time as the tdre flag. consequently, if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt may have priority for acceptance, with the result that the tdre and tend flags are cleared. note that the tei interrupt will not be accepted in this case. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
462 12.5 usage notes the following points should be noted when using the sci. relation between writes to tdr and the tdre flag the tdre flag in ssr is a status flag that indicates that transmit data has been transferred from tdr to tsr. when the sci transfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr regardless of the state of the tdre flag. however, if new data is written to tdr when the tdre flag is cleared to 0, the data stored in tdr will be lost since it has not yet been transferred to tsr. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to tdr. operation when multiple receive errors occur simultaneously if a number of receive errors occur at the same time, the state of the status flags in ssr is as shown in table 12-13. if there is an overrun error, data is not transferred from rsr to rdr, and the receive data is lost. table 12-13 state of ssr status flags and transfer of receive data ssr status flags receive data transfer rdrf orer fer per rsr to rdr receive error status 1100x overrun error 0010 framing error 0001 parity error 1110x overrun error + framing error 1101x overrun error + parity error 0011 framing error + parity error 1111x overrun error + framing error + parity error notes: : receive data is transferred from rsr to rdr. x: receive data is not transferred from rsr to rdr. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
463 break detection and processing (asynchronous mode only): when framing error (fer) detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the parity error flag (per) may also be set. note that, since the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. sending a break (asynchronous mode only): the txd pin has a dual function as an i/o port whose direction (input or output) is determined by dr and ddr. this can be used to send a break. between serial transmission initialization and setting of the te bit to 1, the mark state is replaced by the value of dr (the pin does not function as the txd pin until the te bit is set to 1). consequently, ddr and dr for the port corresponding to the txd pin are first set to 1. to send a break during serial transmission, first clear dr to 0, then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. receive error flags and transmit operations (clocked synchronous mode only): transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. receive data sampling timing and reception margin in asynchronous mode: in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock. this is illustrated in figure 12-21. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
464 internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 12-21 receive data sampling timing in asynchronous mode thus the reception margin in asynchronous mode is given by formula (1) below. m = | (0.5 C 1 2n ) C (l C 0.5) f C | d C 0.5 | n (1 + f) | 100% ... formula (1) where m : reception margin (%) n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. when d = 0.5 and f = 0, m = (0.5 e 1 2 16 ) 100% = 46.875% ... formula (2) however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
465 restrictions on use of dtc when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ? clock cycles after tdr is updated by the dtc. misoperation may occur if the transmit clock is input within 4 ? clocks after tdr is updated. (figure 12-22) when rdr is read by the dtc, be sure to set the activation source to the relevant sci reception end interrupt (rxi). t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when operating on an external clock, set t >4 clocks. tdre figure 12-22 example of clocked synchronous transmission by dtc www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
467 section 13 smart card interface 13.1 overview sci supports an ic card (smart card) interface conforming to iso/iec 7816-3 (identification card) as a serial communication interface extension function. switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 13.1.1 features features of the smart card interface supported by the h8s/2355 are as follows. asynchronous mode ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported on-chip baud rate generator allows any bit rate to be selected three interrupt sources ? three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently ? the transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (dtc) to execute data transfer www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
468 13.1.2 block diagram figure 13-1 shows a block diagram of the smart card interface. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock ? ?/4 ?/16 ?/64 txi rxi eri smr legend scmr rsr rdr tsr tdr smr scr ssr brr : smart card mode register : receive shift register : receive data register : transmit shift register : transmit data register : serial mode register : serial control register : serial status register : bit rate register figure 13-1 block diagram of smart card interface www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
469 13.1.3 pin configuration table 13-1 shows the smart card interface pin configuration. table 13-1 smart card interface pins channel pin name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
470 13.1.4 register configuration table 13-2 shows the registers used by the smart card interface. details of smr, brr, scr, tdr, rdr, and mstpcr are the same as for the normal sci function: see the register descriptions in section 12, serial communication interface. table 13-2 smart card interface registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e 1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 2 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e all module stop control register mstpcr r/w h'3fff h'ff3c notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
471 13.2 register descriptions registers added with the smart card interface and bits for which the function changes are described here. 13.2.1 smart card mode register (scmr) bit:7 65 43 21 0 sdir sinv smif initial value : 1 1 1 1 0 0 1 0 r/w : r/w r/w r/w scmr is an 8-bit readable/writable register that selects the smart card interface function. scmr is initialized to h'f2 by a reset, and in standby mode or module stop mode. bits 7 to 4reserved: read-only bits, always read as 1. bit 3smart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first bit 2smart card data invert (sinv): specifies inversion of the data logic level. this function is used together with the sdir bit for communication with an inverse convention card. the sinv bit does not affect the logic level of the parity bit. for parity-related setting procedures, see section 13.3.4, register settings. bit 2 sinv description 0 tdr contents are transmitted as they are (initial value) receive data is stored as it is in rdr 1 tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
472 bit 1reserved: read-only bit, always read as 1. bit 0smart card interface mode select (smif): enables or disables the smart card interface function. bit 0 smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled 13.2.2 serial status register (ssr) bit:7 65 43 21 0 tdre rdrf orer ers per tend mpb mpbt initial value : 1 0 0 0 0 1 0 0 r/w : r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only 0 can be written to bits 7 to 3, to clear these flags. bit 4 of ssr has a different function in smart card interface mode. coupled with this, the setting conditions for bit 2, tend, are also different. bits 7 to 5 operate in the same way as for the normal sci. for details, see section 12.2.7, serial status register (ssr). bit 4error signal status (ers): in smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. framing errors are not detected in smart card interface mode. bit 4 ers description 0 [clearing condition] (initial value) upon reset, and in standby mode or module stop mode when 0 is written to ers after reading ers = 1 1 [setting condition] when the low level of the error signal is sampled note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
473 bits 3 to 0 operate in the same way as for the normal sci. for details, see section 12.2.7, serial status register (ssr). however, the setting conditions for the tend bit, are as shown below. bit 2 tend description 0 [clearing conditions] (initial value) when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and write data to tdr 1 [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 note: etu: elementary time unit (time for transfer of 1 bit) 13.2.3 serial mode register (smr) bit:7 65 43 21 0 gm chr pe o/ e stop mp cks1 cks0 initial value : 0 0 0 0 0 0 0 0 set value * :gm 0 1 o/ e 1 0 cks1 cks0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w note: * when the smart card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2. the function of bit 7 of smr changes in smart card interface mode. bit 7gsm mode (gm): sets the smart card interface function to gsm mode. this bit is cleared to 0 when the normal smart card interface is used. in gsm mode, this bit is set to 1, the timing of setting of the tend flag that indicates transmission completion is advanced and clock output control mode addition is performed. the contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (scr). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
474 bit 7 gm description 0 normal smart card interface mode operation (initial value) tend flag generation 12.5 etu after beginning of start bit clock output on/off control only 1 gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) note: etu: elementary time unit (time for transfer of 1 bit) bits 6 to 0operate in the same way as for the normal sci. for details, see section 12.2.5, serial mode register (smr). 13.2.4 serial control register (scr) bit:7 65 43 21 0 tie rie te re mpie teie cke1 cke0 initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w in smart card interface mode, the function of bits 1 and 0 of scr changes when bit 7 of the serial mode register (smr) is set to 1. bits 7 to 2operate in the same way as for the normal sci. for details, see section 12.2.6, serial control register (scr). bits 1 and 0clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. in smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
475 scmr smr scr setting smif c/ a , gm cke1 cke0 sck pin function 0 see the sci 1 0 0 0 operates as port i/o pin 1 0 0 1 outputs clock as sck output pin 1 1 0 0 operates as sck output pin, with output fixed low 1 1 0 1 outputs clock as sck output pin 1 1 1 0 operates as sck output pin, with output fixed high 1 1 1 1 outputs clock as sck output pin 13.3 operation 13.3.1 overview the main functions of the smart card interface are as follows. ? one frame consists of 8-bit data plus a parity bit. ? in transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. ? if the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. ? only asynchronous communication is supported; there is no clocked synchronous communication function. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
476 13.3.2 pin connections figure 13-2 shows a schematic diagram of smart card interface related pin connections. in communication with an ic card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected with the lsi pin. the data transmission line should be pulled up to the v cc power supply with a resistor. when the clock generated on the smart card interface is used by an ic card, the sck pin output is input to the clk pin of the ic card. no connection is needed if the ic card uses an internal clock. lsi port output is used as the reset signal. other pins must normally be connected to the power supply or ground. txd rxd sck rx (port) h8s/2355 i/o clk rst v cc connected equipment ic card data line clock line reset line figure 13-2 schematic diagram of smart card interface pin connections note: if an ic card is not connected, and the te and re bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
477 13.3.3 data format figure 13-3 shows the smart card interface data format. in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. if an error signal is sampled during transmission, the same data is retransmitted. ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmitting station output de receiving station output : start bit : data bits : parity bit : error signal legend ds d0 to d7 dp de figure 13-3 smart card interface data format www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
478 the operation sequence is as follows. [1] when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] the transmitting station starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). [3] with the smart card interface, the data line then returns to the high-impedance state. the data line is pulled high with a pull-up resistor. [4] the receiving station carries out a parity check. if there is no parity error and the data is received normally, the receiving station waits for reception of the next data. if a parity error occurs, however, the receiving station outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. the signal line is pulled high again by a pull-up resistor. [5] if the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. if it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
479 13.3.4 register settings table 13-3 shows a bit map of the registers used by the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described below. table 13-3 smart card interface register settings bit register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smr gm 0 1 o/ e 1 0 cks1 cks0 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr tie rie te re 0 0 cke1 * cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf orer ers per tend 0 0 rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scmr sdir sinv smif notes: : unused bit. * : the cke1 bit must be cleared to 0 when the gm bit in smr is cleared to 0. smr setting: the gm bit is cleared to 0 in normal smart card interface mode, and set to 1 in gsm mode. the o/ e bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the on-chip baud rate generator. see section 13.3.5, clock. brr setting: brr is used to set the bit rate. see section 13.3.5, clock, for the method of calculating the value to be set. scr setting: the function of the tie, rie, te, and re bits is the same as for the normal sci. for details, see section 12, serial communication interface. bits cke1 and cke0 specify the clock output. when the gm bit in smr is cleared to 0, set these bits to b'00 if a clock is not to be output, or to b'01 if a clock is to be output. when the gm bit in smr is set to 1, clock output is performed. the clock output can also be fixed high or low. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
480 smart card mode register (scmr) setting: the sdir bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. the sinv bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. the smif bit is set to 1 in the case of the smart card interface. examples of register settings and the waveform of the start character are shown below for the two types of ic card (direct convention and inverse convention). direct convention (sdir = sinv = o/ e = 0) ds d0 d1 d2 d3 d4 d5 d6 d7 dp azzazzzaaz (z) (z) state with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. the start character data above is h'3b. the parity bit is 1 since even parity is stipulated for the smart card. inverse convention (sdir = sinv = o/ e = 1) ds d7 d6 d5 d4 d3 d2 d1 d0 dp azzaaaaaaz (z) (z) state with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first order. the start character data above is h'3f. the parity bit is 0, corresponding to state z, since even parity is stipulated for the smart card. with the h8s/2355, inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in smr is set to odd parity mode (the same applies to both transmission and reception). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
481 13.3.5 clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. the bit rate is set with brr and the cks1 and cks0 bits in smr. the formula for calculating the bit rate is as shown below. table 13-5 shows some sample bit rates. if clock output is selected by setting cke0 to 1, a clock with a frequency of 372 times the bit rate is output from the sck pin. b = ? 1488 2 2ne1 (n + 1) 10 6 where: n = value set in brr (0 n 255) b = bit rate (bit/s) ? = operating frequency (mhz) n = see table 13-4 table 13-4 correspondence between n and cks1, cks0 n cks1 cks0 000 11 210 31 table 13-5 examples of bit rate b (bit/s) for various brr settings (when n = 0) ? (mhz) n 10.00 10.714 13.00 14.285 16.00 18.00 20.00 0 13441 14400 17473 19200 21505 24194 26882 1 6720 7200 8737 9600 10753 12097 13441 2 4480 4800 5824 6400 7168 8065 8961 note: bit rates are rounded to the nearest whole number. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
482 the method of calculating the value to be set in the bit rate register (brr) from the operating frequency and bit rate, on the other hand, is shown below. n is an integer, 0 n 255, and the smaller error is specified. n = ? 1488 2 2ne1 b 10 6 e 1 table 13-6 examples of brr settings for bit rate b (bit/s) (when n = 0) ? (mhz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 bit/s n error n error n error n error n error n error n error n error 9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60 table 13-7 maximum bit rate at various frequencies (smart card interface mode) ? (mhz) maximum bit rate (bit/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 the bit rate error is given by the following formula: error (%) = ( ? 1488 2 2ne1 b (n + 1) 10 6 e 1) 100 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
483 13.3.6 data transfer operations initialization: before transmitting and receiving data, initialize the sci as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] clear the te and re bits in scr to 0. [2] clear the error flags ers, per, and orer in ssr to 0. [3] set the o/ e bit and cks1 and cks0 bits in smr. clear the c/ a , chr, and mp bits to 0, and set the stop and pe bits to 1. [4] set the smif, sdir, and sinv bits in scmr. when the smif bit is set to 1, the txd and rxd pins are both switched from ports to sci pins, and are placed in the high-impedance state. [5] set the value corresponding to the bit rate in brr. [6] set the cke0 bit in scr. clear the tie, rie, te, re, mpie, teie and cke1 bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. [7] wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
484 serial data transmission: as data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal sci. figure 13-4 shows a flowchart for transmitting, and figure 13-5 shows the relation between a transmit operation and the internal registers. [1] perform smart card interface mode initialization as described above in initialization. [2] check that the ers error flag in ssr is cleared to 0. [3] repeat steps [2] and [3] until it can be confirmed that the tend flag in ssr is set to 1. [4] write the transmit data to tdr, clear the tdre flag to 0, and perform the transmit operation. the tend flag is cleared to 0. [5] when transmitting data continuously, go back to step [2]. [6] to end transmission, clear the te bit to 0. with the above processing, interrupt servicing or data transfer by the dtc is possible. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (txi) request will be generated. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (eri) request will be generated. the timing for setting the tend flag depends on the value of the gm bit in smr. the tend flag set timing is shown in figure 13-6. if the dtc is activated by a txi request, the number of bytes set in the dtc can be transmitted automatically, including automatic retransmission. for details, see interrupt operations and data transfer operation by dtc below. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
485 initialization no yes clear te bit to 0 start transmission start no no no yes yes yes yes no end write data to tdr, and clear tdre flag in ssr to 0 error processing error processing tend=1? all data transmitted? tend=1? ers=0? ers=0? figure 13-4 example of transmission processing flow www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
486 (1) data write tdr tsr (shift register) data 1 (2) transfer from tdr to tsr data 1 data 1 ; data remains in tdr (3) serial data output note: when the ers flag is set, it should be cleared until transfer of the last bit (d7 in lsb-first transmission, d0 in msb-first transmission) of the next transfer data to be transmitted has been completed. in case of normal transmission: tend flag is set in case of transmit error: ers flag is set steps (2) and (3) above are repeated until the tend flag is set i/o signal line output data 1 data 1 figure 13-5 relation between transmit operation and internal registers ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5etu txi (tend interrupt) 11.0etu de guard time when gm = 1 legend ds : start bit d0 to d7 : data bits dp : parity bit de : error signal when gm = 0 figure 13-6 tend flag generation timing in transmission operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
487 serial data reception: data reception in smart card mode uses the same processing procedure as for the normal sci. figure 13-7 shows an example of the transmission processing flow. [1] perform smart card interface mode initialization as described above in initialization. [2] check that the orer flag and per flag in ssr are cleared to 0. if either is set, perform the appropriate receive error processing, then clear both the orer and the per flag to 0. [3] repeat steps [2] and [3] until it can be confirmed that the rdrf flag is set to 1. [4] read the receive data from rdr. [5] when receiving data continuously, clear the rdrf flag to 0 and go back to step [2]. [6] to end reception, clear the re bit to 0. initialization read rdr and clear rdrf flag in ssr to 0 clear re bit to 0 start reception start error processing no no no yes yes orer = 0 and per = 0 rdrf=1? all data received? yes figure 13-7 example of reception processing flow www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
488 with the above processing, interrupt servicing or data transfer by the dtc is possible. if reception ends and the rdrf flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (rxi) request will be generated. if an error occurs in reception and either the orer flag or the per flag is set to 1, a transfer error interrupt (eri) request will be generated. if the dtc is activated by an rxi request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the dtc are transferred. for details, see interrupt operation and data transfer operation by dtc below. if a parity error occurs during reception and the per is set to 1, the received data is still transferred to rdr, and therefore this data can be read. mode switching operation: when switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing re bit to 0 and setting te bit to 1. the rdrf flag or the per and orer flags can be used to check that the receive operation has been completed. when switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing te bit to 0 and setting re bit to 1. the tend flag can be used to check that the transmit operation has been completed. fixing clock output level: when the gsm bit in smr is set to 1, the clock output level can be fixed with bits cke1 and cke0 in scr. at this time, the minimum clock pulse width can be made the specified width. figure 13-8 shows the timing for fixing the clock output level. in this example, gsm is set to 1, cke1 is cleared to 0, and the cke0 bit is controlled. sck specified pulse width scr write (cke0 = 0) scr write (cke0 = 1) specified pulse width figure 13-8 timing for fixing clock output level interrupt operation: there are three interrupt sources in smart card interface mode: transmit data empty interrupt (txi) requests, transfer error interrupt (eri) requests, and receive data full interrupt (rxi) requests. the transmit end interrupt (tei) request is not used in this mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
489 when the tend flag in ssr is set to 1, a txi interrupt request is generated. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when any of flags orer, per, and ers in ssr is set to 1, an eri interrupt request is generated. the relationship between the operating states and interrupt sources is shown in table 13-8. table 13-8 smart card mode operating states and interrupt sources operating state flag enable bit interrupt source dmac activation dtc activation transmit mode normal operation tend tie txi possible possible error ers rie eri not possible not possible receive mode normal operation rdrf rie rxi possible possible error per, orer rie eri not possible not possible data transfer operation by dtc: in smart card mode, as with the normal sci, transfer can be carried out using the dtc. in a transmit operation, the tdre flag is also set to 1 at the same time as the tend flag in ssr, and a txi interrupt is generated. if the txi request is designated beforehand as a dtc activation source, the dtc will be activated by the txi request, and transfer of the transmit data will be carried out. the tdre and tend flags are automatically cleared to 0 when data transfer is performed by the dtc. in the event of an error, the sci retransmits the same data automatically. however, the ers flag is not cleared automatically when an error occurs, and so the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. when performing transfer using the dtc, it is essential to set and enable the dtc before carrying out sci setting. for details of the dtc setting procedures, see section 7, data transfer controller (dtc). in a receive operation, an rxi interrupt request is generated when the rdrf flag in ssr is set to 1. if the rxi request is designated beforehand as a dtc activation source, the dtc will be activated by the rxi request, and transfer of the receive data will be carried out. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dtc. if an error occurs, an error flag is set but the rdrf flag is not. consequently, the dtc is not activated, but instead, an eri interrupt request is sent to the cpu. therefore, the error flag should be cleared. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
490 13.3.7 operation in gsm mode switching the mode: when switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. ? when changing from smart card interface mode to software standby mode [1] set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the value for the fixed output state in software standby mode. [2] write 0 to the te bit and re bit in the serial control register (scr) to halt transmit/receive operation. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. [3] write 0 to the cke0 bit in scr to halt the clock. [4] wait for one serial clock period. during this interval, clock output is fixed at the specified level, with the duty preserved. [5] write h'00 to smr and scmr. [6] make the transition to the software standby state. ? when returning to smart card interface mode from software standby mode [7] exit the software standby state. [8] set the cke1 bit in scr to the value for the fixed output state (current sck pin state) when software standby mode is initiated. [9] set smart card interface mode and output the clock. signal generation is started with the normal duty. [1] [2] [3] [4] [5] [6] [7] [8] [9] software standby normal operation normal operation figure 13-9 clock halt and restart procedure www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
491 powering on: to secure the clock duty from power-on, the following switching procedure should be followed. [1] the initial state is port input and high impedance. use a pull-up resistor or pull-down resistor to fix the potential. [2] fix the sck pin to the specified output level with the cke1 bit in scr. [3] set smr and scmr, and switch to smart card mode operation. [4] set the cke0 bit in scr to 1 to start clock output. 13.4 usage notes the following points should be noted when using the sci as a smart card interface. receive data sampling timing and reception margin in smart card interface mode: in smart card interface mode, the sci operates on a basic clock with a frequency of 372 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 186th pulse of the basic clock. this is illustrated in figure 13-10. internal basic clock 372 clocks 186 clocks receive data (rxd) synchro- nization sampling timing d0 d1 data sampling timing 185 371 0 371 185 0 0 start bit figure 13-10 receive data sampling timing in smart card mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
492 thus the reception margin in asynchronous mode is given by the following formula. m = (0.5 e 1 2n ) e (l e 0.5) f e d e 0.5 n (1 + f ) 100% where m: reception margin (%) n: ratio of bit rate to clock (n = 372) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation assuming values of f = 0 and d = 0.5 in the above formula, the reception margin formula is as follows. when d = 0.5 and f = 0, m = (0.5 e 1/2 372) 100% = 49.866% retransfer operations: retransfer operations are performed by the sci in receive mode and transmit mode as described below. retransfer operation when sci is in receive mode figure 13-11 illustrates the retransfer operation when the sci is in receive mode. [1] if an error is found when the received parity bit is checked, the per bit in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the per bit in ssr should be kept cleared to 0 until the next parity bit is sampled. [2] the rdrf bit in ssr is not set for a frame in which an error has occurred. [3] if no error is found when the received parity bit is checked, the per bit in ssr is not set to 1. [4] if no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the rdrf flag in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an rxi interrupt request is generated. if dtc data transfer by an rxi source is enabled, the contents of rdr can be read automatically. when the rdr data is read by the dtc, the rdrf flag is automatically cleared to 0. [5] when a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
493 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame rdrf [1] per [2] [3] [4] figure 13-11 retransfer operation in sci receive mode retransfer operation when sci is in transmit mode figure 13-12 illustrates the retransfer operation when the sci is in transmit mode. [6] if an error signal is sent back from the receiving end after transmission of one frame is completed, the ers bit in ssr is set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the ers bit in ssr should be kept cleared to 0 until the next parity bit is sampled. [7] the tend bit in ssr is not set for a frame for which an error signal indicating an abnormality is received. [8] if an error signal is not sent back from the receiving end, the ers bit in ssr is not set. [9] if an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the tend bit in ssr is set to 1. if the tie bit in scr is enabled at this time, a txi interrupt request is generated. if data transfer by the dtc by means of the txi source is enabled, the next data can be written to tdr automatically. when data is written to tdr by the dtc, the tdre bit is automatically cleared to 0. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame tdre tend [6] fer/ers transfer to tsr from tdr [7] [9] [8] transfer to tsr from tdr transfer to tsr from tdr figure 13-12 retransfer operation in sci transmit mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
495 section 14 a/d converter 14.1 overview the h8s/2355 series incorporates a successive approximation type 10-bit a/d converter that allows up to eight analog input channels to be selected. 14.1.1 features a/d converter features are listed below 10-bit resolution eight input channels settable analog conversion voltage range ? conversion of analog voltages with the reference voltage pin (v ref ) as the analog reference voltage high-speed conversion ? minimum conversion time: 6.7 s per channel (at 20 mhz operation) choice of single mode or scan mode ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels four data registers ? conversion results are held in a 16-bit data register for each channel sample and hold function three kinds of conversion start ? choice of software or timer conversion start trigger (tpu or 8-bit timer), or adtrg pin a/d conversion end interrupt generation ? a/d conversion end interrupt (adi) request can be generated at the end of a/d conversion module stop mode can be set ? as the initial setting, a/d converter operation is halted. register access is enabled by exiting module stop mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
496 14.1.2 block diagram figure 14-1 shows a block diagram of the a/d converter. module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt bus interface a d c s r a d c r a d d r d a d d r c a d d r b a d d r a av cc v ref av ss an0 an1 an2 an3 an4 an5 an6 an7 adtrg conversion start trigger from 8-bit timer or tpu successive approximations register multiplexer adcr adcsr addra addrb addrc addrd : a/d control register : a/d control/status register : a/d data register a : a/d data register b : a/d data register c : a/d data register d figure 14-1 block diagram of a/d converter www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
497 14.1.3 pin configuration table 14-1 summarizes the input pins used by the a/d converter. the av cc and av ss pins are the power supply pins for the analog block in the a/d converter. the v ref pin is the a/d conversion reference voltage pin. the eight analog input pins are divided into two groups: group 0 (an0 to an3), and group 1 (an4 to an7). table 14-1 a/d converter pins pin name symbol i/o function analog power supply pin av cc input analog block power supply analog ground pin av ss input analog block ground and a/d conversion reference voltage reference voltage pin v ref input a/d conversion reference voltage analog input pin 0 an0 input group 0 analog inputs analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input group 1 analog inputs analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
498 14.1.4 register configuration table 14-2 summarizes the registers of the a/d converter. table 14-2 a/d converter registers name abbreviation r/w initial value address * 1 a/d data register ah addrah r h'00 h'ff90 a/d data register al addral r h'00 h'ff91 a/d data register bh addrbh r h'00 h'ff92 a/d data register bl addrbl r h'00 h'ff93 a/d data register ch addrch r h'00 h'ff94 a/d data register cl addrcl r h'00 h'ff95 a/d data register dh addrdh r h'00 h'ff96 a/d data register dl addrdl r h'00 h'ff97 a/d control/status register adcsr r/(w) * 2 h'00 h'ff98 a/d control register adcr r/w h'3f h'ff99 module stop control register mstpcr r/w h'3fff h'ff3c notes: 1. lower 16 bits of the address. 2. bit 7 can only be written with 0 for flag clearing. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
499 14.2 register descriptions 14.2.1 a/d data registers a to d (addra to addrd) 15 ad9 0 r bit initial value r/w : : : 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r there are four 16-bit read-only addr registers, addra to addrd, used to store the results of a/d conversion. the 10-bit data resulting from a/d conversion is transferred to the addr register for the selected channel and stored there. the upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of addr, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. bits 5 to 0 are always read as 0. the correspondence between the analog input channels and addr registers is shown in table 14- 3. addr can always be read by the cpu. the upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (temp). for details, see section 14.3, interface to bus master. the addr registers are initialized to h'0000 by a reset, and in standby mode or module stop mode. table 14-3 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
500 14.2.2 a/d control/status register (adcsr) 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w bit initial value r/w : : : note: * only 0 can be written to bit 7, to clear this flag. adcsr is an 8-bit readable/writable register that controls a/d conversion operations and shows the status of the operation. adcsr is initialized to h'00 by a reset, and in hardware standby mode or module stop mode. bit 7a/d end flag (adf): status flag that indicates the end of a/d conversion. bit 7 adf description 0 [clearing conditions] (initial value) when 0 is written to the adf flag after reading adf = 1 when the dtc is activated by an adi interrupt and addr is read 1 [setting conditions] single mode: when a/d conversion ends scan mode: when a/d conversion ends on all specified channels bit 6a/d interrupt enable (adie): selects enabling or disabling of interrupt (adi) requests at the end of a/d conversion. bit 6 adie description 0 a/d conversion end interrupt (adi) request disabled (initial value) 1 a/d conversion end interrupt (adi) request enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
501 bit 5a/d start (adst): selects starting or stopping on a/d conversion. holds a value of 1 during a/d conversion. the adst bit can be set to 1 by software, a timer conversion start trigger, or the a/d external trigger input pin ( adtrg ). bit 5 adst description 0 a/d conversion stopped (initial value) 1 single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. bit 4scan mode (scan): selects single mode or scan mode as the a/d conversion operating mode. see section 14.4, operation, for single mode and scan mode operation. only set the scan bit while conversion is stopped (adst = 0). bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3clock select (cks): sets the a/d conversion time. only change the conversion time while conversion is stopped (adst = 0). bit 3 cks description 0 conversion time = 266 states (max.) (initial value) 1 conversion time = 134 states (max.) bits 2 to 0channel select 2 to 0 (ch2 to ch0): together with the scan bit, these bits select the analog input channels. only set the input channel while conversion is stopped (adst = 0). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
502 group selection channel selection description ch2 ch1 ch0 single mode scan mode 0 0 0 an0 (initial value) an0 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3 1 0 0 an4 an4 1 an5 an4, an5 1 0 an6 an4 to an6 1 an7 an4 to an7 14.2.3 a/d control register (adcr) 7 trgs1 0 r/w 6 trgs0 0 r/w 5 1 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion operations. adcr is initialized to h'3f by a reset, and in standby mode or module stop mode. bits 7 and 6timer trigger select 1 and 0 (trgs1, trgs0): select enabling or disabling of the start of a/d conversion by a trigger signal. only set bits trgs1 and trgs0 while conversion is stopped (adst = 0). bit 7 bit 6 trgs1 trgs0 description 0 0 a/d conversion start by external trigger is disabled (initial value) 1 a/d conversion start by external trigger (tpu) is enabled 1 0 a/d conversion start by external trigger (8-bit timer) is enabled 1 a/d conversion start by external trigger pin ( adtrg ) is enabled bits 5 to 0reserved: these bits are reserved; they are always read as 1 and cannot be modified. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
503 14.2.4 module stop control register (mstpcr) 15 0 r/w bit initial value r/w : : : 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl mstpcr is a 16-bit readable/writable register that performs module stop mode control. when the mstp9 bit in mstpcr is set to 1, a/d converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 19.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 9module stop (mstp9): specifies the a/d converter module stop mode. bit 9 mstp9 description 0 a/d converter module stop mode cleared 1 a/d converter module stop mode set (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
504 14.3 interface to bus master addra to addrd are 16-bit registers, and the data bus to the bus master is 8 bits wide. therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (temp). a data read from addr is performed as follows. when the upper byte is read, the upper byte value is transferred to the cpu and the lower byte value is transferred to temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading addr. always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 14-2 shows the data flow for addr access. bus master (h'aa) addrnh (h'aa) addrnl (h'40) lower byte read addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) module data bus module data bus bus interface upper byte read bus master (h'40) bus interface figure 14-2 addr access operation (reading h'aa40) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
505 14.4 operation the a/d converter operates by successive approximation with 10-bit resolution. it has two operating modes: single mode and scan mode. 14.4.1 single mode (scan = 0) single mode is selected when a/d conversion is to be performed on a single channel only. a/d conversion is started when the adst bit is set to 1, according to the software or external trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. on completion of conversion, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. the adf flag is cleared by writing 0 after reading adcsr. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when channel 1 (an1) is selected in single mode are described next. figure 14-3 shows a timing diagram for this example. [1] single mode is selected (scan = 0), input channel an1 is selected (ch2 = 0, ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). [2] when a/d conversion is completed, the result is transferred to addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. [3] since adf = 1 and adie = 1, an adi interrupt is requested. [4] the a/d interrupt handling routine starts. [5] the routine reads adcsr, then writes 0 to the adf flag. [6] the routine reads and processes the connection result (addrb). [7] execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps [2] to [7] are repeated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
506 adie adst adf state of channel 0 (an0) a/d conversion starts 2 1 addra addrb addrc addrd state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) note: * vertical arrows ( ) indicate instructions executed by software. set * set * clear * clear * a/d conversion result 1 a/d conversion a/d conversion result 2 read conversion result read conversion result idle idle idle idle idle idle a/d conversion set * figure 14-3 example of a/d converter operation (single mode, channel 1 selected) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
507 14.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by a software, timer or external trigger input, a/d conversion starts on the first channel in the group (an0). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the addr registers corresponding to the channels. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when three channels (an0 to an2) are selected in scan mode are described next. figure 14-4 shows a timing diagram for this example. [1] scan mode is selected (scan = 1), scan group 0 is selected (ch2 = 0), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1) [2] when a/d conversion of the first channel (an0) is completed, the result is transferred to addra. next, conversion of the second channel (an1) starts automatically. [3] conversion proceeds in the same way through the third channel (an2). [4] when conversion of all the selected channels (an0 to an2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. [5] steps [2] to [4] are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
508 adst adf addra addrb addrc addrd state of channel 0 (an0) state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) set * 1 clear * 1 idle notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. clear * 1 idle idle a/d conversion time idle continuous a/d conversion execution a/d conversion 1 idle idle idle idle idle transfer * 2 a/d conversion 3 a/d conversion 2 a/d conversion 5 a/d conversion 4 a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion result 4 figure 14-4 example of a/d converter operation (scan mode, channels an0 to an2 selected) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
509 14.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 14-5 shows the a/d conversion timing. table 14-4 indicates the a/d conversion time. as indicated in figure 14-5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 14-4. in scan mode, the values given in table 14-4 apply to the first conversion time. in the second and subsequent conversions the conversion time is fixed at 256 states when cks = 0 or 128 states when cks = 1. (1) (2) t d t spl t conv ? input sampling timing adf address bus write signal legend (1) : adcsr write cycle (2) : adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 14-5 a/d conversion timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
510 table 14-4 a/d conversion time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max a/d conversion start delay t d 1017 6 9 input sampling time t spl 63 31 a/d conversion time t conv 259 266 131 134 note: values in the table are the number of states. 14.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs1 and trgs0 bits are set to 11 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as if the adst bit has been set to 1 by software. figure 14-6 shows the timing. ? adtrg internal trigger signal adst a/d conversion figure 14-6 external trigger input timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
511 14.5 interrupts the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. adi interrupt requests can be enabled or disabled by means of the adie bit in adcsr. the dtc can be activated by an adi interrupt. having the converted data read by the dtc in response to an adi interrupt enables continuous conversion to be achieved without imposing a load on software. the a/d converter interrupt source is shown in table 14-5. table 14-5 a/d converter interrupt source interrupt source description dtc activation adi interrupt due to end of conversion possible 14.6 usage notes the following points should be noted when using the a/d converter. setting range of analog power supply and other pins: (1) analog input voltage range the voltage applied to analog input pins an0 to an7 during a/d conversion should be in the range av ss ann v ref . (2) relation between av cc , av ss and v cc , v ss as the relationship between av cc , av ss and v cc , v ss , set av ss = v ss . if the a/d converter is not used, the av cc and av ss pins must on no account be left open. (3) v ref input range the analog reference voltage input at the v ref pin set in the range v ref av cc . if conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. notes on board design: in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
512 also, digital circuitry must be isolated from the analog input signals (an0 to an7), analog reference power supply (v ref ), and analog power supply (av cc ) by the analog ground (av ss ). also, the analog ground (av ss ) should be connected at one point to a stable digital ground (v ss ) on the board. notes on noise countermeasures: a protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an7) and analog reference power supply (v ref ) should be connected between av cc and av ss as shown in figure 14-7. also, the bypass capacitors connected to av cc and v ref and the filter capacitor connected to an0 to an7 must be connected to av ss . if a filter capacitor is connected as shown in figure 14-7, the input currents at the analog input pins (an0 to an7) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the current input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding the circuit constants. av cc * 1 * 1 v ref an0 to an7 av ss notes: values are reference values. 1. 2. r in : input impedance r in * 2 100 0.1 f 0.01 f 10 f figure 14-7 example of analog input protection circuit www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
513 20 pf to a/d converter an0 to an7 10 k note: values are reference values. figure 14-8 analog input pin equivalent circuit a/d conversion precision definitions: h8s/2355 series a/d conversion precision definitions are given below. resolution the number of a/d converter digital output codes offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 14-10). full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 14-10). quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 14-9). nonlinearity error the error with respect to the ideal a/d conversion characteristic between the zero voltage and the full-scale voltage. does not include the offset error, full-scale error, or quantization error. absolute precision the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
514 111 110 101 100 011 010 001 000 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 1 1024 2 1024 1022 1024 1023 1024 figure 14-9 a/d conversion precision definitions (1) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
515 fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 14-10 a/d conversion precision definitions (2) permissible signal source impedance: h8s/2355 series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k w or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k w , charging may be insufficient and it may not be possible to guarantee the a/d conversion precision. however, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k w , and the signal source impedance is ignored. however, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/s or greater). when converting a high-speed analog signal, a low-impedance buffer should be inserted. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
516 influences on absolute precision: adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd such as av ss . care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. a/d converter equivalent circuit h8/2355 series 20 pf c in = 15 pf 10 k to 10 k low-pass filter c to 0.1 f sensor output impedance sensor input note: values are reference values. figure 14-11 example of analog input circuit www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
517 section 15 d/a converter (not supported in h8s/2393) 15.1 overview the h8s/2355 and h8s/2353 include a two-channel d/a converter. 15.1.1 features d/a converter features are listed below 8-bit resolution two output channels maximum conversion time of 10 s (with 20 pf load) output voltage of 0 v to v ref d/a output hold function in software standby mode module stop mode can be set ? as the initial setting, d/a converter operation is halted. register access is enabled by exiting module stop mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
518 15.1.2 block diagram figure 15-1 shows a block diagram of the d/a converter. module data bus internal data bus v ref av cc da1 da0 av ss 8-bit d/a control circuit dadr0 bus interface dadr1 dacr figure 15-1 block diagram of d/a converter www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
519 15.1.3 pin configuration table 15-1 summarizes the input and output pins of the d/a converter. table 15-1 pin configuration pin name symbol i/o function analog power pin av cc input analog power source analog ground pin av ss input analog ground and reference voltage analog output pin 0 da0 output channel 0 analog output analog output pin 1 da1 output channel 1 analog output reference voltage pin v ref input analog reference voltage 15.1.4 register configuration table 15-2 summarizes the registers of the d/a converter. table 15-2 d/a converter registers name abbreviation r/w initial value address * d/a data register 0 dadr0 r/w h'00 h'ffa4 d/a data register 1 dadr1 r/w h'00 h'ffa5 d/a control register dacr r/w h'1f h'ffa6 module stop control register mstpcr r/w h'3fff h'ff3c note: * lower 16 bits of the address. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
520 15.2 register descriptions 15.2.1 d/a data registers 0 and 1 (dadr0, dadr1) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : dadr0 and dadr1 are 8-bit readable/writable registers that store data for conversion. whenever output is enabled, the values in dadr0 and dadr1 are converted and output from the analog output pins. dadr0 and dadr1 are each initialized to h'00 by a reset and in hardware standby mode. 15.2.2 d/a control register (dacr) 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : dacr is an 8-bit readable/writable register that controls the operation of the d/a converter. dacr is initialized to h'1f by a reset and in hardware standby mode. bit 7d/a output enable 1 (daoe1): controls d/a conversion and analog output for channel 1. bit 7 daoe1 description 0 analog output da1 is disabled (initial value) 1 channel 1 d/a conversion is enabled; analog output da1 is enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
521 bit 6d/a output enable 0 (daoe0): controls d/a conversion and analog output for channel 0. bit 6 daoe0 description 0 analog output da0 is disabled (initial value) 1 channel 0 d/a conversion is enabled; analog output da0 is enabled bit 5d/a enable (dae): the daoe0 and daoe1 bits both control d/a conversion. when the dae bit is cleared to 0, the channel 0 and 1 d/a conversions are controlled independently. when the dae bit is set to 1, the channel 0 and 1 d/a conversions are controlled together. output of resultant conversions is always controlled independently by the daoe0 and daoe1 bits. bit 7 bit 6 bit 5 daoe1 daoe0 dae description 00 * channel 0 and 1 d/a conversions disabled 1 0 channel 0 d/a conversion enabled channel 1 d/a conversion disabled 1 channel 0 and 1 d/a conversions enabled 1 0 0 channel 0 d/a conversion disabled channel 1 d/a conversion enabled 1 channel 0 and 1 d/a conversions enabled 1 * channel 0 and 1 d/a conversions enabled * : dont care if the h8s/2355 series enters software standby mode when d/a conversion is enabled, the d/a output is held and the analog power current is the same as during d/a conversion. when it is necessary to reduce the analog power current in software standby mode, clear both the daoe0 and daoe1 bits to 0 to disable d/a output. bits 4 to 0reserved: read-only bits, always read as 1. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
522 15.2.3 module stop control register (mstpcr) 15 0 r/w bit initial value r/w : : : 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl mstpcr is a 16-bit readable/writable register that performs module stop mode control. in the h8s/2355 and h8s/2353, when the mstp10 bit in mstpcr is set to 1, d/a converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 19.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 10module stop (mstp10): specifies the d/a converter module stop mode. bit 10 mstp10 description 0 d/a converter module stop mode cleared 1 d/a converter module stop mode set (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
523 15.3 operation the d/a converter includes d/a conversion circuits for two channels, each of which can operate independently. d/a conversion is performed continuously while enabled by dacr. if either dadr0 or dadr1 is written to, the new data is immediately converted. the conversion result is output by setting the corresponding daoe0 or daoe1 bit to 1. the operation example described in this section concerns d/a conversion on channel 0. figure 15-2 shows the timing of this operation. [1] write the conversion data to dadr0. [2] set the daoe0 bit in dacr to 1. d/a conversion is started and the da0 pin becomes an output pin. the conversion result is output after the conversion time has elapsed. the output value is expressed by the following formula: dadr contents 256 v ref the conversion results are output continuously until dadr0 is written to again or the daoe0 bit is cleared to 0. [3] if dadr0 is written to again, the new data is immediately converted. the new conversion result is output after the conversion time has elapsed. [4] if the daoe0 bit is cleared to 0, the da0 pin becomes an input pin. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
524 conversion data 1 conversion result 1 high-impedance state t dconv dadr0 write cycle da0 daoe0 dadr0 address ? dacr write cycle conversion data 2 conversion result 2 t dconv legend t dconv : d/a conversion time dadr0 write cycle dacr write cycle figure 15-2 example of d/a converter operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
525 section 16 ram 16.1 overview the h8s/2355 and h8s/2393 have 4 kbytes of on-chip high-speed static ram, and the h8s/2353 has 2 kbytes. the ram is connected to the cpu by a 16-bit data bus, enabling one-state access by the cpu to both byte data and word data. this makes it possible to perform fast word data transfer. the on-chip ram can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr). 16.1.1 block diagram figure 16-1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffec00 h'ffec02 h'ffec04 h'fffbfe h'ffec01 h'ffec03 h'ffec05 h'fffbff figure 16-1 block diagram of ram (h8s/2355) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
526 16.1.2 register configuration the on-chip ram is controlled by syscr. table 16-1 shows the address and initial value of syscr. table 16-1 ram register name abbreviation r/w initial value address * system control register syscr r/w h'01 h'ff39 note: * lower 16 bits of the address. 16.2 register descriptions 16.2.1 system control register (syscr) 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 0 1 0 r/w bit initial value r/w : : : the on-chip ram is enabled or disabled by the rame bit in syscr. for details of other bits in syscr, see section 3.2.2, system control register (syscr). bit 0ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
527 16.3 operation when the rame bit is set to 1, accesses to addresses h'ffec00 to h'fffbff are directed to the on-chip ram. when the rame bit is cleared to 0, the off-chip address space is accessed. since the on-chip ram is connected to the cpu by an internal 16-bit data bus, it can be written to and read in byte or word units. each type of access can be performed in one state. even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. word data must start at an even address. 16.4 usage note dtc register information can be located in addresses h'fff800 to h'fffbff. when the dtc is used, the rame bit must not be cleared to 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
529 section 17 rom 17.1 overview the h8s/2355 has 128 kbytes of on-chip rom (prom or mask rom). the h8s/2353 has 64 kbytes of on-chip mask rom, and the h8s/2393 has 32 kbytes of on-chip mask rom. the rom is connected to the h8s/2000 cpu by a 16-bit data bus. the cpu accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. the on-chip rom is enabled or disabled by setting the mode pins (md 2 , md 1 , and md 0 ) and bit eae in bcrl. the prom version of the h8s/2355 series can be programmed with a general-purpose prom programmer, by setting prom mode. 17.1.1 block diagram figure 17-1 shows a block diagram of the on-chip rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'01fffe h'000001 h'000003 h'01ffff h'00fffe h'010000 h'010002 h'00ffff h'010001 h'010003 when eae= 0 figure 17-1 block diagram of rom (h8s/2355) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
530 17.1.2 register configuration the h8s/2355s on-chip rom is controlled by bcrl. the register configuration is shown in table 17-1. table 17-1 rom register initial value name abbreviation r/w power-on reset manual reset address * bus control register l bcrl r/w h'3c retained h'fed5 note: * lower 16 bits of the address. 17.2 register descriptions 17.2.1 bus control register l (bcrl) 7 brle 0 r/w 6 0 r/w 5 eae 1 r/w 4 1 r/w 3 1 r/w 0 waite 0 r/w 2 1 r/w 1 0 r/w bit initial value r/w : : : enabling or disabling of part of the h8s/2355? on-chip rom area can be selected by means of the eae bit in bcrl. for details of the other bits in bcrl, see 6.2.5, bus control register l. bit 5external address enable (eae): selects whether addresses h'010000 to h'01ffff are to be internal addresses or external addresses. this setting is invalid in normal mode. bit 5 eae description 0 addresses h'010000 to h'01ffff are in on-chip rom (in the h8s/2355) or a reserved area * (in the h8s/2353). 1 addresses h'010000 to h'01ffff are external addresses (external expansion mode) or a reserved area * (single-chip mode). (initial value) note: * reserved areas should not be accessed. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
531 17.3 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data can be accessed in one state. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address. the on-chip rom is enabled and disabled by setting the mode pins (md 2 , md 1 , and md 0 ) and bit eae in bcrl. these settings are shown in table 17-2. in normal mode, a maximum of 56 kbytes of rom can be used. table 17-2 operating modes and rom area mode pin bcrl operating mode md 2 md 1 md 0 eae on-chip rom mode 1 normal expanded mode with on-chip rom disabled 0 0 1 disabled mode 2 normal expanded mode with on-chip rom enabled 1 0 enabled (56 kbytes) mode 3 normal single-chip mode 1 mode 4 advanced expanded mode with on-chip rom disabled 1 0 0 disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with 1 0 0 enabled * on-chip rom enabled 1 enabled (64 kbytes) mode 7 advanced single-chip mode 1 0 enabled * 1 enabled (64 kbytes) note: * 128 kbytes in the h8s/2355, 64 kbytes in the h8s/2353, 32 kbytes in the h8s/2393 in h8/2355 modes 6 and 7, the on-chip rom available after a power-on reset is the 64- kbyte area comprising addresses h000000 to h00ffff. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
532 17.4 prom mode 17.4.1 prom mode setting the prom version of the h8s/2355 series suspends its microcontroller functions when placed in prom mode, enabling the on-chip prom to be programmed. this programming can be done with a prom programmer set up in the same way as for the hn27c101 eprom (v pp = 12.5 v). use of a socket adapter to convert from 120 or 128 pins to 32 pins enables programming with a commercial prom programmer. note that the prom programmer should not be set to page mode as the h8s/2355 series does not support page programming. table 17-3 shows how prom mode is selected. table 17-3 selecting prom mode pin names setting md 2 , md 1 , md 0 low stby pa 2 , pa 1 high 17.4.2 socket adapter and memory map programs can be written and verified by attaching a socket adapter to convert from 120 or 128 pins to 32 pins to the prom programmer. table 17-4 gives ordering information for the socket adapter, and figure 17-2 shows the wiring of the socket adapter. figure 17-3 shows the memory map in prom mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
533 tfp-120 73 43 44 45 46 48 49 50 51 2 3 4 5 7 8 9 10 11 74 13 14 16 17 18 19 20 86 12 87 1, 33, 52, 76, 81 93 94 21 22 6, 15, 24, 38, 47, 59, 79, 104 103 75 113 114 115 pin res pd 0 pd 1 pd 2 pd 3 pd 4 pd 5 pd 6 pd 7 pc 0 pc 1 pc 2 pc 3 pc 4 pc 5 pc 6 pc 7 pb 0 nmi pb 2 pb 3 pb 4 pb 5 pb 6 pb 7 pa 0 pf 2 pb 1 pf 1 v cc av cc v ref pa 1 pa 2 v ss av ss stby md 0 md 1 md 2 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ea 15 ea 16 ce oe pgm v cc v ss h8s/2355 series eprom socket note: pins not shown in this figure should be left open. v pp eo 7 to eo 0 ea 16 to ea 0 oe ce pgm : programming power supply (12.5 v) : data input/output : address input : output enable : chip enable : program fp-128 81 49 50 51 52 54 55 56 57 6 7 8 9 11 12 13 14 15 82 17 18 20 21 22 23 24 94 16 95 1, 39, 58, 84, 89 103 104 25 26 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100,114 113 83 123 124 125 hn27c101 (32 pins) figure 17-2 wiring of 120-pin/32-pin socket adapter www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
534 table 17-4 socket adapter microcontroller package socket adapter h8s/2355 120 pin tqfp (tfp-120) hs2655esns1h 128 pin qfp (fp-128) hs2655eshs1h on-chip prom addresses in mcu mode addresses in prom mode h'000000 h'01ffff h'00000 h'1ffff figure 17-3 memory map in prom mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
535 17.5 programming 17.5.1 overview table 17-5 shows how to select the program, verify, and program-inhibit modes in prom mode. table 17-5 mode selection in prom mode pins mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 program l h l v pp v cc data input address input verify l l h v pp v cc data output address input program-inhibit lllv pp v cc high impedance address input lhh hl l hhh legend l : low voltage level h : high voltage level v pp : v pp voltage level v cc : v cc voltage level programming and verification should be carried out using the same specifications as for the standard hn27c101 eprom. however, do not set the prom programmer to page mode does not support page programming. a prom programmer that only supports page programming cannot be used. when choosing a prom programmer, check that it supports high-speed programming in byte units. always set addresses within the range h'00000 to h'0ffff. 17.5.2 programming and verification an efficient, high-speed programming procedure can be used to program and verify prom data. this procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. it leaves the data h'ff in unused addresses. figure 17-4 shows the basic high-speed programming flowchart. tables 17-6 and 17-7 list the electrical characteristics of the chip during programming. figure 17-5 shows a timing chart. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
536 start set programming/verification mode address = 0 verification ok? yes no n = 0 n + 1 ? n program with t pw = 0.2 ms 5% program with t opw = 0.2n ms last address? set read mode v cc = 5.0 v 0.25 v v pp = v cc all addresses read? v cc = 6.0v 0.25v, v pp = 12.5v 0.3v yes no no yes go address + 1 ? address n<25 end fail no go figure 17-4 high-speed programming flowchart www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
537 table 17-6 dc characteristics in prom mode (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min typ max unit test conditions input high voltage eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm v ih 2.4 v cc + 0.3 v input low voltage eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm v il C0.3 0.8 v output high voltage eo 7 to eo 0 v oh 2.4 v i oh = C200 a output low voltage eo 7 to eo 0 v ol 0.45 v i ol = 1.6 ma input leakage current eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm | i li | 2 a v in = 5.25 v/0.5 v v cc current i cc 40 ma v pp current i pp 40 ma www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
538 table 17-7 ac characteristics in prom mode (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25c 5c) item symbol min typ max unit test conditions address setup time t as 2 s figure 17-5 * 1 oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df * 2 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite programming t opw * 3 0.19 5.25 ms v cc setup time t vcs 2 s ce setup time t ces 2 s data output delay time t oe 0 150 ns notes: 1. input pulse level: 0.8 v to 2.2 v input rise time and fall time 20 ns timing reference levels: input: 1.0 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined to be when output has reached the open state, and the output level can no longer be referenced. 3. t opw is defined by the value shown in the flowchart. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
539 program verify input data output data t as t ah t df t dh t ds t vps t vcs t ces t pw t opw * t oes t oe address data v pp v cc ce pgm oe v pp v cc v cc +1 v cc note: * t opw is defined by the value shown in the flowchart. figure 17-5 prom programming/verification timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
540 17.5.3 programming precautions program using the specified voltages and timing. the programming voltage (v pp ) in prom mode is 12.5 v. if the prom programmer is set to hitachi hn27c101 specifications, v pp will be 12.5 v. applied voltages in excess of the specified values can permanently destroy the mcu. be particularly careful about the prom programmer?s overshoot characteristics. before programming, check that the mcu is correctly mounted in the prom programmer. overcurrent damage to the mcu can result if the index marks on the prom programmer, socket adapter, and mcu are not correctly aligned. do not touch the socket adapter or mcu while programming. touching either of these can cause contact faults and programming errors. the mcu cannot be programmed in page programming mode. select the programming mode carefully. the size of the h8s/2355 prom is 128 kbytes. always set addresses within the range h'00000 to h'0ffff. during programming, write h'ff to unused addresses to avoid verification errors. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
541 17.5.4 reliability of programmed data an effective way to assure the data retention characteristics of the programmed chips is to bake them at 150c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 17-6 shows the recommended screening procedure. mount program chip and verify data bake chip for 24 to 48 hours at 125 c to 150 c with power off read and check program figure 17-6 recommended screening procedure if a series of programming errors occurs while the same prom programmer is being used, stop programming and check the prom programmer and socket adapter for defects. please inform hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
543 section 18 clock pulse generator 18.1 overview the h8s/2355 series has a built-in clock pulse generator (cpg) that generates the system clock (?), the bus master clock, and internal clocks. the clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium- speed clock divider, and a bus master clock selection circuit. 18.1.1 block diagram figure 18-1 shows a block diagram of the clock pulse generator. extal xtal duty adjustment circuit oscillator medium- speed divider system clock to ?pin internal clock to supporting modules bus master clock to cpu and dtc ?2 to ?32 sck2 to sck0 sckcr bus master clock selection circuit figure 18-1 block diagram of clock pulse generator 18.1.2 register configuration the clock pulse generator is controlled by sckcr. table 18-1 shows the register configuration. table 18-1 clock pulse generator register name abbreviation r/w initial value address * system clock control register sckcr r/w h'00 h'ff3a note: * lower 16 bits of the address. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
544 18.2 register descriptions 18.2.1 system clock control register (sckcr) 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs ?clock output control and medium- speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): controls ? output. description bit 7 software hardware pstop normal operation sleep mode standby mode standby mode 0 ? output (initial value) ? output fixed high high impedance 1 fixed high fixed high fixed high high impedance bit 6reserved: this bit can be read or written to, but only 0 should be written. bits 5 to 3reserved: read-only bits, always read as 0. bits 2 to 0system clock select 2 to 0 (sck2 to sck0): these bits select the clock for the bus master. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is ?/2 1 0 medium-speed clock is ?/4 1 medium-speed clock is ?/8 1 0 0 medium-speed clock is ?/16 1 medium-speed clock is ?/32 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
545 18.3 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 18.3.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 18-2. select the damping resistance r d according to table 18-2. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22pf figure 18-2 connection of crystal resonator (example) table 18-2 damping resistance value frequency (mhz) 248121620 r d ( w ) 1k 500 200 0 0 0 crystal resonator: figure 18-3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 18-3 and the same resonance frequency as the system clock (?). xtal c l at-cut parallel-resonance type extal c 0 lr s figure 18-3 crystal resonator equivalent circuit www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
546 table 18-3 crystal resonator parameters frequency (mhz) 248121620 r s max ( w ) 500 120 80 60 50 40 c 0 max (pf) 777777 note on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. see figure 18-4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. c l2 signal a signal b c l1 h8s/2355 xtal extal avoid figure 18-4 example of incorrect board design www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
547 18.3.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 18-5. if the xtal pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode. extal xtal external clock input open (a) xtal pin left open extal xtal external clock input ( b ) com p lementar y clock in p ut at xtal p in figure 18-5 external clock input (examples) external clock: the external clock signal should have the same frequency as the system clock (?). table 18-4 and figure 18-6 show the input conditions for the external clock. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
548 table 18-4 external clock input conditions v cc = 2.7 v to 5.5 v v cc = 5.0 v 10% item symbol min max min max unit test conditions external clock input low pulse width t exl 40 20 ns figure 18-6 external clock input high pulse width t exh 40 20 ns external clock rise time t exr 10 5 ns external clock fall time t exf 10 5 ns clock low pulse width t cl 0.4 0.6 0.4 0.6 t cyc ? 3 5 mhz figure 20-4 level 80 80 ns ? < 5 mhz clock high pulse width t ch 0.4 0.6 0.4 0.6 t cyc ? 3 5 mhz level 80 80 ns ? < 5 mhz t exh t exl t exr t exf v cc 0.5 extal figure 18-6 external clock input timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
549 18.4 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (?). 18.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate ?/2, ?/4, ?/8, ?/16, and ?/32. 18.6 bus master clock selection circuit the bus master clock selection circuit selects the system clock (?) or one of the medium-speed clocks (?/2, ?/4, or ?/8, ?/16, and ?/32) to be supplied to the bus master, according to the settings of the sck2 to sck0 bits in sckcr. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
551 section 19 power-down modes 19.1 overview in addition to the normal program execution state, the h8s/2355 series has five power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. the h8s/2355 series operating modes are as follows: (1) high-speed mode (2) medium-speed mode (3) sleep mode (4) module stop mode (5) software standby mode (6) hardware standby mode of these, (2) to (6) are power-down modes. sleep mode is a cpu mode, medium-speed mode is a cpu and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the cpu). a combination of these modes can be set. after a reset, the h8s/2355 series is in high-speed mode. table 19-1 shows the conditions for transition to the various modes, the status of the cpu, on-chip supporting modules, etc., and the method of clearing each mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
552 table 19-1 operating modes operating transition clearing cpu modules mode condition condition oscillator registers registers i/o ports high speed mode control register functions high speed functions high speed functions high speed medium- speed mode control register functions medium speed functions high/ medium speed * 1 functions high speed sleep mode instruction interrupt functions halted retained high speed functions high speed module stop mode control register functions high/ medium speed functions halted retained/ reset * 2 retained software standby mode instruction external interrupt halted halted retained halted retained/ reset * 2 retained hardware standby mode pin halted halted undefined halted reset high impedance notes: 1. the bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. the sci and a/d converter are reset, and other on-chip supporting modules retain their state. 19.1.1 register configuration power-down modes are controlled by the sbycr, sckcr, and mstpcr registers. table 19-2 summarizes these registers. table 19-2 power-down mode registers name abbreviation r/w initial value address * standby control register sbycr r/w h'08 h'ff38 system clock control register sckcr r/w h'00 h'ff3a module stop control register h mstpcrh r/w h'3f h'ff3c module stop control register l mstpcrl r/w h'ff h'ff3d note: * lower 16 bits of the address. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
553 19.2 register descriptions 19.2.1 standby control register (sbycr) 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 0 r/w 2 0 1 0 bit initial value r/w : : : sbycr is an 8-bit readable/writable register that performs software standby mode control. sbycr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7software standby (ssby): specifies a transition to software standby mode. remains set to 1 when software standby mode is released by an external interrupt, and a transition is made to normal operation. the ssby bit should be cleared by writing 0 to it. bit 7 ssby description 0 transition to sleep mode after execution of sleep instruction (initial value) 1 transition to software standby mode after execution of sleep instruction bits 6 to 4standby timer select 2 to 0 (sts2 to sts0): these bits select the time the mcu waits for the clock to stabilize when software standby mode is cleared by an external interrupt. with crystal oscillation, refer to table 19-4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). with an external clock, any selection can be made. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states (initial value) 1 standby time = 16384 states 1 0 standby time = 32768 states 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 standby time = 262144 states 1 0 reserved 1 standby time = 16 states www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
554 bit 3output port enable (ope): specifies whether the output of the address bus and bus control signals ( cs0 to cs7 , as , rd , hwr , lwr ) is retained or set to the high-impedance state in software standby mode. bit 3 ope description 0 in software standby mode, address bus and bus control signals are high-impedance 1 in software standby mode, address bus and bus control signals retain output state (initial value) bits 2 and 1reserved: read-only bits, always read as 0. bit 0reserved: this bit can be read or written to, but only 0 should be written. 19.2.2 system clock control register (sckcr) 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs ?clock output control and medium- speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): controls ? output. description bit 7 normal operating software standby hardware standby pstop mode sleep mode mode mode 0 ? output (initial value) ? output fixed high high impedance 1 fixed high fixed high fixed high high impedance bits 6reserved: this bit can be read or written to, but only 0 should be written. bits 5 to 3reserved: read-only bits, always read as 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
555 bits 2 to 0system clock select (sck2 to sck0): these bits select the clock for the bus master. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master in high-speed mode (initial value) 1 medium-speed clock is ?/2 1 0 medium-speed clock is ?/4 1 medium-speed clock is ?/8 1 0 0 medium-speed clock is ?/16 1 medium-speed clock is ?/32 1 19.2.3 module stop control register (mstpcr) 15 0 r/w bit initial value r/w : : : 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl mstpcr is a 16-bit readable/writable register that performs module stop mode control. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 15 to 0module stop (mstp 15 to mstp 0): these bits specify module stop mode. see table 19-3 for the method of selecting on-chip supporting modules. bits 15 to 0 mstp15 to mstp0 description 0 module stop mode cleared 1 module stop mode set www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
556 19.3 medium-speed mode when the sck2 to sck0 bits in sckcr are set to 1, the operating mode changes to medium- speed mode as soon as the current bus cycle ends. in medium-speed mode, the cpu operates on the operating clock (?/2, ?/4, ?/8, ?/16, or ?/32) specified by the sck2 to sck0 bits. the bus masters other than the cpu (the dtc) also operate in medium-speed mode. on-chip supporting modules other than the bus masters always operate on the high-speed clock (?). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if ?/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. if a sleep instruction is executed when the ssby bit in sbycr is set to 1, a transition is made to software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the res pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. the same applies in the case of a reset caused by overflow of the watchdog timer. when the stby pin is driven low, a transition is made to hardware standby mode. figure 19-1 shows the timing for transition to and clearance of medium-speed mode. ? bus master clock supporting module clock internal address bus internal write signal medium-speed mode sckcr sckcr figure 19-1 medium-speed mode transition and clearance timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
557 19.4 sleep mode if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, the cpu enters sleep mode. in sleep mode, cpu operation stops but the contents of the cpus internal registers are retained. other supporting modules do not stop. sleep mode is cleared by a reset or any interrupt, and the cpu returns to the normal program execution state via the exception handling state. sleep mode is not cleared if interrupts are disabled, or if interrupts other than nmi are masked by the cpu. when the stby pin is driven low, a transition is made to hardware standby mode. 19.5 module stop mode 19.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. table 19-3 shows mstp bits and the corresponding on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci and a/d converter are retained. after reset clearance, all modules other than dtc are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. if a transition is made to sleep mode when all modules are stopped (mstpcr = h'ffff), or modules other than the 8-bit timers are stopped (mstpcr = h'efff), operation of the bus controller and i/o ports is also halted, enabling current dissipation to be further reduced. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
558 table 19-3 mstp bits and corresponding on-chip supporting modules register bit module mstpcrh mstp15 mstp14 data transfer controller (dtc) mstp13 16-bit timer pulse unit (tpu) mstp12 8-bit timer mstp11 mstp10 d/a converter * mstp9 a/d converter mstp8 mstpcrl mstp7 serial communication interface (sci) channel 2 mstp6 serial communication interface (sci) channel 1 mstp5 serial communication interface (sci) channel 0 mstp4 mstp3 mstp2 mstp1 mstp0 note: bits 15, 11, 8, and 4 to 0 can be read or written to, but do not affect operation. * in the h8s/2393 bit 10 can be read and written to but has no effect on operation, as a d/a converter is not supported. 19.5.2 usage notes dtc module stop: depending on the operating status of the dtc, the mstp14 bit may not be set to 1. setting of the dtc module stop mode should be carried out only when the respective module is not activated. for details, refer to section 7, data transfer controller (dtc). on-chip supporting module interrupt: relevant interrupt operations cannot be performed in module stop mode. consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. interrupts should therefore be disabled before entering module stop mode. writing to mstpcr: mstpcr should only be written to by the cpu. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
559 19.6 software standby mode 19.6.1 software standby mode if a sleep instruction is executed when the ssby bit in sbycr is set to 1, software standby mode is entered. in this mode, the cpu, on-chip supporting modules, and oscillator all stop. however, the contents of the cpus internal registers, ram data, and the states of on-chip supporting modules other than the sci and a/d converter, and i/o ports, are retained. whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the ope bit in sbycr. in this mode the oscillator stops, and therefore power dissipation is significantly reduced. 19.6.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq2 ), or by means of the res pin or stby pin. clearing with an interrupt when an nmi or irq0 to irq2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits sts2 to sts0 in syscr, stable clocks are supplied to the entire h8s/2355 series chip, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq2 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq2 is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side or has been designated as a dtc activation source. clearing with the res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire h8s/2355 series chip. note that the res pin must be held low until clock oscillation stabilizes. when the res pin goes high, the cpu begins reset exception handling. clearing with the stby pin when the stby pin is driven low, a transition is made to hardware standby mode. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
560 19.6.3 setting oscillation stabilization time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. using a crystal oscillator: set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation stabilization time). table 19-4 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 19-4 oscillation stabilization time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 0 0 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 4.1 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2 1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2 16.4 1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4 32.8 1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 65.5 1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2 1 0 reserved 1 16 states 0.8 1.0 1.3 1.6 2.0 2.7 4.0 8.0 s : recommended time setting using an external clock: any value can be set. normally, use of the minimum time is recommended. 19.6.4 software standby mode application example figure 19-2 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
561 oscillator nmi nmieg ssby nmi exception handling nmieg=1 ssby=1 sleep instruction software standby mode (power-down mode) oscillation stabilization time t osc2 nmi exception handling figure 19-2 software standby mode application example 19.6.5 usage notes i/o port status: in software standby mode, i/o port states are retained. if the ope bit is set to 1, the address bus and bus control signal output is also retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. current dissipation during oscillation stabilization wait period: current dissipation increases during the oscillation stabilization wait period. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
562 19.7 hardware standby mode 19.7.1 hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md 2 to md 0 ) while the h8s/2355 series is in hardware standby mode. hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillator stabilizes (at least 8 ms?the oscillation stabilization time?when using a crystal oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 19.7.2 hardware standby mode timing figure 19-3 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation stabilization time, then changing the res pin from low to high. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
563 oscillator res stby oscillation stabilization time reset exception handling figure 19-3 hardware standby mode timing (example) 19.8 ? clock output disabling function output of the ? clock can be controlled by means of the pstop bit in sckcr, and ddr for the corresponding port. when the pstop bit is set to 1, the ? clock stops at the end of the bus cycle, and ? output goes high. ? clock output is enabled when the pstop bit is cleared to 0. when ddr for the corresponding port is cleared to 0, ? clock output is disabled and input port mode is set. table 19-5 shows the state of the ? pin in each processing state. table 19-5 ? pin state in each processing state ddr 0 1 pstop 0 1 hardware standby mode high impedance software standby mode high impedance fixed high sleep mode high impedance ? output fixed high normal operating state high impedance ? output fixed high www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
565 section 20 electrical characteristics 20.1 absolute maximum ratings table 20-1 lists the absolute maximum ratings. table 20-1 absolute maximum ratings item symbol value unit power supply voltage v cc C0.3 to +7.0 v programming voltage v pp C0.3 to +13.5 v input voltage (except port 4) v in C0.3 to v cc +0.3 v input voltage (port 4) v in C0.3 to av cc +0.3 v reference voltage v ref C0.3 to av cc +0.3 v analog power supply voltage av cc C0.3 to +7.0 v analog input voltage v an C0.3 to av cc +0.3 v operating temperature t opr regular specifications: C20 to +75 c wide-range specifications: C40 to +85 c storage temperature t stg C55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
566 20.2 dc characteristics table 20-2 lists the dc characteristics. table 20-3 lists the permissible output currents. table 20-2 dc characteristics (1) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v* 1 , t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) item symbol min typ max unit test conditions schmitt port 2, v t C 1.0 v trigger input p6 4 to p6 7 , v t + v cc 0.7 v voltage pa 4 to pa 7 v t + C v t C 0.4 v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc C 0.7 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v port 1, 3, 5, b to g, p6 0 to p6 3 , pa 0 to pa 3 2.0 v cc + 0.3 v port4 2.0 av cc + 0.3 v input low voltage res , stby , md 2 to md 0 v il C0.3 0.5 v nmi, extal, port 1, 3 to 5, b to g, p6 0 to p6 3 , pa 0 to pa 3 C0.3 0.8 v output high all output pins v oh v cc C 0.5 v i oh = C200 a voltage 3.5 v i oh = C1 ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage port 1, a to c 1.0 v i ol = 10 ma input leakage res | i in | 10.0 a v in = current stby , nmi, md 2 to md 0 1.0 a 0.5 to v cc C 0.5 v port 4 1.0 a v in = 0.5 to av cc C 0.5 v www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
567 item symbol min typ max unit test conditions three-state leakage current (off state) port 1 to 3, 5, 6, a to g ? i tsi ? 1.0 a v in = 0.5 to v cc C 0.5 v mos input pull-up current port a to e Ci p 50 300 a v in = 0 v input res c in 80 pf v in = 0 v capacitance nmi 50 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25c current dissipation * 2 normal operation i cc * 4 60 (5.0 v) 89 ma f = 20 mhz sleep mode 40 (5.0 v) 73 ma f = 20 mhz standby 0.01 5.0 a t a 50c mode * 3 20 50c < t a analog power supply current during a/d and d/a conversion al cc 0.8 (5.0 v) 2.0 ma idle 0.01 5.0 a reference current during a/d and d/a conversion al cc 1.9 (5.0 v) 3.0 ma idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used,do not leave the av cc , av ss , and v ref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 2. current dissipation values are for v ih min = v cc C0.5 v and v il max = 0.5v with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. the values are for v ram v cc < 4.5v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 0.80 (ma/(mhz v)) v cc f [normal mode] i cc max = 1.0 (ma) + 0.65 (ma/(mhz v)) v cc f [sleep mode] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
568 table 20-2 dc characteristics (2) conditions: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v* 1 , t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltage port 2, p6 4 to p6 7 , pa 4 to pa 7 v t C v t + v t + C v t C v cc 0.2 v cc 0.07 v cc 0.7 v v v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc 0.9 v cc +0.3 v extal v cc 0.7 v cc +0.3 v port 1, 3, 5, b to g, p6 0 to p6 3 , pa 0 to pa 3 v cc 0.7 v cc +0.3 v port 4 v cc 0.7 av cc +0.3 v input low voltage res , stby , md 2 to md 0 v il C0.3 v cc 0.1 v nmi, extal, port 1, 3 to 5, b to g, p6 0 to p6 3 , C0.3 v cc 0.2 v v cc < 4.0 v pa 0 to pa 3 0.8 v cc = 4.0 to 5.5 v output high all output pins v oh v cc C 0.5 v i oh = C200 a voltage v cc C 1.0 v i oh = C1 ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage port 1, a to c 1.0 v v cc 4 v i ol = 5 ma 4.0 < v cc 5.5 v i ol = 10 ma input leakage res | i in | 10.0 a v in = current stby , nmi, md 2 to md 0 1.0 a 0.5 to v cc C 0.5v port 4 1.0 a v in = 0.5 to av cc C 0.5v www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
569 item symbol min typ max unit test conditions three-state leakage current (off state) port 1 to 3, 5, 6, a to g ? i tsi ? 1.0 a v in = 0.5 to v cc C0.5 v mos input pull-up current port a to e Ci p 10 300 a v cc = 2.7 v to 5.5 v, v in = 0 v input res c in 80 pf v in = 0 v capacitance nmi 50 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25c current dissipation * 2 normal operation i cc * 4 18 (3.0 v) 45 ma f = 10 mhz sleep mode 11 (3.0 v) 37 ma f = 10 mhz standby 0.01 5.0 a t a 50c mode * 3 20 50c < t a analog power supply current during a/d and d/a conversion al cc 0.2 (3.0 v) 2.0 ma idle 0.01 5.0 a reference current during a/d and d/a conversion al cc 1.2 (3.0 v) 3.0 ma idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used,do not leave the av cc , av ss , and vref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 2. current dissipation values are for v ih min = v cc C0.5 v and v il max = 0.5v with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 0.80 (ma/(mhz v)) v cc f [normal mode] i cc max = 1.0 (ma) + 0.65 (ma/(mhz v)) v cc f [sleep mode] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
570 table 20-2 dc characteristics (3) conditions: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v* 1 , t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltage port 2, p6 4 to p6 7 , pa 4 to pa 7 v t C v t + v t + C v t C v cc 0.2 v cc 0.07 v cc 0.7 v v v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc 0.9 v cc +0.3 v extal v cc 0.7 v cc +0.3 v port 1, 3, 5, b to g, p6 0 to p6 3 , pa 0 to pa 3 v cc 0.7 v cc +0.3 v port 4 v cc 0.7 av cc +0.3 v input low voltage res , stby , md 2 to md 0 v il C0.3 v cc 0.1 v nmi, extal, port 1, 3 to 5, b to g, p6 0 to p6 3 , C0.3 v cc 0.2 v v cc < 4.0 v pa 0 to pa 3 0.8 v cc = 4.0 to 5.5 v output high all output pins v oh v cc C 0.5 v i oh = C200 a voltage v cc C 1.0 v i oh = C1 ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage port 1, a to c 1.0 v v cc 4 v i ol = 5 ma 4.0 < v cc 5.5 v i ol = 10 ma input leakage res | i in | 10.0 a v in = current stby , nmi, md 2 to md 0 1.0 a 0.5 to v cc C 0.5v port 4 1.0 a v in = 0.5 to av cc C 0.5v www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
571 item symbol min typ max unit test conditions three-state leakage current (off state) port 1 to 3, 5, 6, a to g ? i tsi ? 1.0 a v in = 0.5 to v cc C0.5 v mos input pull-up current port a to e Ci p 10 300 a v cc = 3.0 v to 5.5 v, v in = 0 v input res c in 80 pf v in = 0 v capacitance nmi 50 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25c current dissipation * 2 normal operation i cc * 4 25 (3.3 v) 58 ma f = 13 mhz sleep mode 16 (3.3 v) 48 ma f = 13 mhz standby 0.01 5.0 a t a 50c mode * 3 20.0 50c < t a analog power supply current during a/d and d/a conversion al cc 0.2 (3.3 v) 2.0 ma idle 0.01 5.0 a reference current during a/d and d/a conversion al cc 1.2 (3.3 v) 3.0 ma idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used,do not leave the av cc , av ss , and vref pins open. connect av cc and v ref to v cc , and connect av ss to v ss . 2. current dissipation values are for v ih min = v cc C0.5 v and v il max = 0.5v with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. the values are for v ram v cc < 3.0 v, v ih min = v cc 0.9, and v il max = 0.3v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 0.80 (ma/(mhz v)) v cc f [normal mode] i cc max = 1.0 (ma) + 0.65 (ma/(mhz v)) v cc f [sleep mode] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
572 table 20-3 permissible output currents conditions: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to av cc , v ss = av ss = 0 v, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) item symbol min typ max unit permissible output port 1, a to c i ol 10ma low current (per pin) other output pins 2.0 ma permissible output low current (total) total of 32 pins including port 1 and a to c ? i ol 80ma total of all output pins, including the above 120 ma permissible output high current (per pin) all output pins Ci oh 2.0 ma permissible output high current (total) total of all output pins ? Ci oh 40ma notes: 1. to protect chip reliability, do not exceed the output current values in table 20-3. 2. when driving a darlington pair or led directly, always insert a current-limiting resistor in the output line, as show in figures 20-1 and 20-2. 2k w h8s/2355 series port darlin g ton pair figure 20-1 darlington pair drive circuit (example) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
573 600 w h8s/2355 series port 1, a to c led figure 20-2 led drive circuit (example) 20.3 ac characteristics figure 20-3 show, the test conditions for the ac characteristics. c lsi output pin r h r l c = 90 pf: port 1, a to f c = 30 pf: port 2, 3, 5, 6, g r l = 2.4 k w r h = 12 k w i/o timing test levels low level: 0.8 v high level: 2.0 v 5 v figure 20-3 output load circuit www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
574 20.3.1 clock timing table 20-4 lists the clock timing table 20-4 clock timing condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ? = 2 to 10 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ? = 2 to 20 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c: (mask rom version only) v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ? = 2 to 13 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition a condition b condition c test item symbol min max min max min max unit conditions clock cycle time t cyc 100 500 50 500 76 500 ns figure 20-4 clock high pulse width t ch 35 20 23 ns figure 20-4 clock low pulse width t cl 35 20 23 ns clock rise time t cr 15 5 15 ns clock fall time t cf 15 5 15 ns clock oscillator setting time at reset (crystal) t osc1 20 10 20 ms figure 20-5 clock oscillator setting time in software standby (crystal) t osc2 8 8 20 ms figure 19-2 external clock output stabilization delay time t dext 500 500 500 s figure 20-5 t ch t cf t cyc t cl t cr figure 20-4 system clock timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
575 t osc1 t osc1 extal nmi v cc stby res t dext t dext figure 20-5 oscillator settling timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
576 20.3.2 control signal timing table 20-5 lists the control signal timing. table 20-5 control signal timing condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ? = 2 to 10 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ? = 2 to 20 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c: (mask rom version only) v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ? = 2 to 13 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition a condition b condition c test item symbol min max min max min max unit conditions res setup time t ress 200 200 200 ns figure 20-6 res pulse width t resw 20 20 20 t cyc nmi reset setup time t nmirs 250 200 250 ns nmi reset hold time t nmirh 200 200 200 nmi setup time t nmis 250 150 250 ns figure 20-7 nmi hold time t nmih 10 10 10 nmi pulse width (exiting software standby mode) t nmiw 200 200 200 ns irq setup time t irqs 250 150 250 ns irq hold time t irqh 10 10 10 ns irq pulse width (exiting software standby mode) t irqw 200 200 200 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
577 t ress t resw t nmirh t nmirs t ress res nmi figure 20-6 reset input timing t irqs t nmis t nmih irq edge input nmi t irqs t irqh irqi (i= 0 to 2) irq level input t nmiw t irqw figure 20-7 interrupt input timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
578 20.3.3 bus timing table 20-6 lists the bus timing. table 20-6 bus timing condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ? = 2 to 10 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ?= 2 to 20 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c: (mask rom version only) v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ? = 2 to 13 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition a condition b condition c test item symbol min max min max min max unit conditions address delay time t ad 40 20 40 ns figure 20-8 to address setup time t as 0.5 t cyc C 30 0.5 t cyc C 15 0.5 t cyc C 30 ns figure 20-12 address hold time t ah 0.5 t cyc C 20 0.5 t cyc C 10 0.5 t cyc C 20 ns cs delay time 1 t csd1 40 20 40ns as delay time t asd 40 20 40ns rd delay time 1 t rsd1 40 20 40ns rd delay time 2 t rsd2 40 20 40ns read data setup time t rds 30 15 30 ns read data hold time t rdh 000ns read data access time1 t acc1 1.0 t cyc C 50 1.0 t cyc C 25 1.0 t cyc C 50 ns read data access time2 t acc2 1.5 t cyc C 50 1.5 t cyc C 25 1.5 t cyc C 50 ns read data access time3 t acc3 2.0 t cyc C 50 2.0 t cyc C 25 2.0 t cyc C 50 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
579 condition a condition b condition c test item symbol min max min max min max unit conditions read data access time 4 t acc4 2.5 t cyc C 50 2.5 t cyc C 25 2.5 t cyc C 50 ns figure 20-8 to figure 20-12 read data access time 5 t acc5 3.0 t cyc C 50 3.0 t cyc C 25 3.0 t cyc C 50 ns wr delay time 1 t wrd1 40 20 40ns wr delay time 2 t wrd2 40 20 40ns wr pulse width 1 t wsw1 1.0 t cyc C 40 1.0 t cyc C 20 1.0 t cyc C 40 ns wr pulse width 2 t wsw2 1.5 t cyc C 40 1.5 t cyc C 20 1.5 t cyc C 40 ns write data delay time t wdd 60 30 60ns write data setup time t wds 0.5 t cyc C 40 0.5 t cyc C 20 0.5 t cyc C 33 ns write data hold time t wdh 0.5 t cyc C 20 0.5 t cyc C 10 0.5 t cyc C 20 ns wait setup time t wts 60 30 60 ns figure 20-10 wait hold time t wth 10510ns breq setup time t brqs 60 30 60 ns figure 20-13 back delay time t bacd 30 15 30ns bus-floating time t bzd 100 50 75 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
580 t rsd2 t 1 t ad as a 23 to a 0 t asd rd (read) t 2 t csd1 t as t asd t acc2 t as t as t rsd1 t acc3 t rds t rdh t wrd2 t wdd t wsw1 t wdh t ah cs7 to cs0 d 15 to d 0 (read) hwr , lwr (write) d 15 to d 0 (write) t ah t wrd2 figure 20-8 basic bus timing (two-state access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
581 t rsd2 t 2 as a 23 to a 0 t asd rd (read) t 3 t as t ah t asd t acc4 t rsd1 t acc5 t as t rds t rdh t wrd1 t wrd2 t wds t wsw2 t wdh t ah cs7 to cs0 d 15 to d 0 (read) hwr , lwr (write) d 15 to d 0 (write) t 1 t csd1 t wdd t ad figure 20-9 basic bus timing (three-state access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
582 t w as a 23 to a 0 rd (read) t 3 cs7 to cs0 d 15 to d 0 (read) hwr , lwr (write) d 15 to d 0 (write) t 2 t wts t 1 t wth t wts t wth wait figure 20-10 basic bus timing (three-state access with one wait state) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
583 t rsd2 t 1 as a 23 to a 0 t 2 t ah t acc3 t rds cs7 to cs0 d 15 to d 0 (read) t 2 or t 3 t as t 1 t asd t asd t rdh t ad rd (read) figure 20-11 burst rom access timing (two-state access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
584 t rsd2 t 1 as a 23 to a 0 t 1 t acc1 cs7 to cs0 d 15 to d 0 (read) t 2 or t 3 t rdh t ad rd (read) t rds figure 20-12 burst rom access timing (one-state access) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
585 breq a 23 to a 0 , cs7 to cs0 , t brqs t bacd t bzd t bacd t bzd t brqs back as , rd , hwr , lwr figure 20-13 external bus release timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
586 20.3.4 timing of on-chip supporting modules table 20-7 lists the timing of on-chip supporting modules. table 20-7 timing of on-chip supporting modules condition a: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ? = 2 to 10 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ? = 2 to 20 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c: (mask rom version only) v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ? = 2 to 13 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition a condition b condition c test item symbol min max min max min max unit conditions i/o port output data delay time t pwd 100 50 75 ns figure 20-14 input data setup time t prs 50 30 50 input data hold time t prh 50 30 50 tpu timer output delay time t tocd 100 50 75 ns figure 20-15 timer input setup time t tics 50 30 50 timer clock input setup time t tcks 50 30 50 ns figure 20-16 timer clock single edge t tckwh 1.5 1.5 1.5 t cyc pulse width both edges t tckwl 2.5 2.5 2.5 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
587 condition a condition b condition c test item symbol min max min max min max unit conditions tmr timer output delay time t tmod 100 50 75 ns figure 20-17 timer reset input setup time t tmrs 50 30 50 ns figure 20-19 timer clock input setup time t tmcs 50 30 50 ns figure 20-18 timer clock single edge t tmcwh 1.5 1.5 1.5 t cyc figure 20-18 pulse width both edges t tmcwl 2.5 2.5 2.5 wdt overflow output delay time t wovd 100 50 75 ns figure 20-20 sci input clock asynchro- nous t scyc 444t cyc figure 20-21 cycle synchro- nous 666 input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr 1.5 1.5 1.5 t cyc input clock fall time t sckf 1.5 1.5 1.5 transmit data delay time t txd 100 50 75 ns figure 20-22 receive data setup time (synchronous) t rxs 100 50 75 ns receive data hold time (synchronous) t rxh 100 50 75 ns a/d converter trigger input setup time t trgs 50 30 50 ns figure 20-23 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
588 port 1 to 6, a to g (read) t 2 t 1 t pwd t prh t prs port 1 to 3, 5, 6, a to g (write) figure 20-14 i/o port input/output timing t tics t tocd output compare output * input capture input * note: * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 20-15 tpu input/output timing t tcks t tcks tclka to tclkd t tckwh t tckwl figure 20-16 tpu clock input timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
589 tmo0, tmo1 t tmod figure 20-17 8-bit timer output timing tmci0, tmci1 t tmcs t tmcs t tmcwh t tmcwl figure 20-18 8-bit timer clock input timing tmri0, tmri1 t tmrs figure 20-19 8-bit timer reset input timing wdtovf t wovd t wovd figure 20-20 wdt output timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
590 sck0 to sck2 t sckw t sckr t sckf t scyc figure 20-21 sck clock input timing txd0 to txd2 transit data rxd0 to rxd2 receive data sck0 to sck2 t rxs t rxh t txd figure 20-22 sci input/output timing (clock synchronous mode) adtrg t trgs figure 20-23 a/d converter external trigger input timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
591 20.4 a/d conversion characteristics table 20-8 lists the a/d conversion characteristics. table 20-8 a/d conversion characteristics condition a: v cc = av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ? = 2 to 10 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b: v cc = av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ? = 2 to 20 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c: (mask rom version only) v cc = av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ? = 2 to 13 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition a condition b condition c item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time 13.4 6.7 10.4 s analog input capacitance 20 20 20 pf permissible signal-source 10 * 1 10 * 3 10 * 1 k w impedance 5 * 2 5 * 4 5 * 5 nonlinearity error 7.5 3.5 7.5 lsb offset error 7.5 3.5 7.5 lsb full-scale error 7.5 3.5 7.5 lsb quantization 0.5 0.5 0.5 lsb absolute accuracy 8.0 4.0 8.0 lsb notes: 1. 4.0 v av cc 5.5 v 2. 2.7 v av cc < 4.0 v 3. ? 12 mhz 4. ? > 12 mhz 5. 3.0 v av cc < 4.0 v www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
592 20.5 d/a convervion characteristics table 20-9 lists the d/a conversion characteristics. table 20-9 d/a conversion characteristics condition a: v cc = av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ? = 2 to 10 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b: v cc = av cc = 5.0 v 10%, v ref = 4.5 v to av cc , v ss = av ss = 0 v, ? = 2 to 20 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c: (mask rom version only) v cc = av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ? = 2 to 13 mhz, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition a condition b condition c item min typ max min typ max min typ max unit test conditions resolution 8 8 8 8 8 8 888bit conversion time 10 10 10 s 20-pf capacitive load absolute accuracy 2.0 3.0 1.0 1.5 2.0 3.0 lsb 2-m w resistive load 2.0 1.0 2.0 lsb 4-m w resistive load 20.6 usage note although both the ztat and mask rom versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip rom, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. therefore, if a system is evaluated using the ztat version, a similar evaluation should also be performed using the mask rom version. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
593 appendix a instruction set a.1 instruction list operand notation rd general register (destination) * 1 rs general register (source) * 1 rn general register * 1 ern general register (32-bit register) mac multiply-and-accumulate register (32-bit register) * 2 (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + add C subtract multiply divide logical and logical or ? logical exclusive or ? transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ? logical not (logical complement) ( ) < > contents of operand :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length notes: 1. general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). 2. the mac register cannot be used in the h8s/2355 series. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
594 condition code notation symbol changes according to the result of instruction * undetermined (no guaranteed value) 0 always cleared to 0 1 always set to 1 not affected by execution of the instruction www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
595 table a-1 instruction set (1) data transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic mov mov.b #xx:8,rd b 2 mov.b rs,rd b 2 mov.b @ers,rd b 2 mov.b @(d:16,ers),rd b 4 mov.b @(d:32,ers),rd b 8 mov.b @ers+,rd b 2 mov.b @aa:8,rd b 2 mov.b @aa:16,rd b 4 mov.b @aa:32,rd b 6 mov.b rs,@erd b 2 mov.b rs,@(d:16,erd) b 4 mov.b rs,@(d:32,erd) b 8 mov.b rs,@-erd b 2 mov.b rs,@aa:8 b 2 mov.b rs,@aa:16 b 4 mov.b rs,@aa:32 b 6 mov.w #xx:16,rd w 4 mov.w rs,rd w 2 mov.w @ers,rd w 2 #xx:8 ? rd8 0 1 rs8 ? rd8 0 1 @ers ? rd8 0 2 @(d:16,ers) ? rd8 0 3 @(d:32,ers) ? rd8 0 5 @ers ? rd8,ers32+1 ? ers32 0 3 @aa:8 ? rd8 0 2 @aa:16 ? rd8 0 3 @aa:32 ? rd8 0 4 rs8 ? @erd 0 2 rs8 ? @(d:16,erd) 0 3 rs8 ? @(d:32,erd) 0 5 erd32-1 ? erd32,rs8 ? @erd 0 3 rs8 ? @aa:8 0 2 rs8 ? @aa:16 0 3 rs8 ? @aa:32 0 4 #xx:16 ? rd16 0 2 rs16 ? rd16 0 1 @ers ? rd16 0 2 operation condition code normal ihnzvc advanced no. of states * 1 ??????????????????? ??????????????????? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
596 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic mov mov.w @(d:16,ers),rd w 4 mov.w @(d:32,ers),rd w 8 mov.w @ers+,rd w 2 mov.w @aa:16,rd w 4 mov.w @aa:32,rd w 6 mov.w rs,@erd w 2 mov.w rs,@(d:16,erd) w 4 mov.w rs,@(d:32,erd) w 8 mov.w rs,@-erd w 2 mov.w rs,@aa:16 w 4 mov.w rs,@aa:32 w 6 mov.l #xx:32,erd l 6 mov.l ers,erd l 2 mov.l @ers,erd l 4 mov.l @(d:16,ers),erd l 6 mov.l @(d:32,ers),erd l 10 mov.l @ers+,erd l 4 mov.l @aa:16,erd l 6 mov.l @aa:32,erd l 8 @(d:16,ers) ? rd16 ? ? 0 ? 3 @(d:32,ers) ? rd16 ? ? 0 ? 5 @ers ? rd16,ers32+2 ? ers32 ? ? 0 ? 3 @aa:16 ? rd16 ? ? 0 ? 3 @aa:32 ? rd16 ? ? 0 ? 4 rs16 ? @erd ? ? 0 ? 2 rs16 ? @(d:16,erd) ? ? 0 ? 3 rs16 ? @(d:32,erd) ? ? 0 ? 5 erd32-2 ? erd32,rs16 ? @erd ? ? 0 ? 3 rs16 ? @aa:16 ? ? 0 ? 3 rs16 ? @aa:32 ? ? 0 ? 4 #xx:32 ? erd32 ? ? 0 ? 3 ers32 ? erd32 ? ? 0 ? 1 @ers ? erd32 ? ? 0 ? 4 @(d:16,ers) ? erd32 ? ? 0 ? 5 @(d:32,ers) ? erd32 ? ? 0 ? 7 @ers ? erd32,ers32+4 ? ers32 ?? 0 ? 5 @aa:16 ? erd32 ? ? 0 ? 5 @aa:32 ? erd32 ? ? 0 ? 6 operation condition code normal ihnzvc advanced no. of states * 1 ??????????????????? ??????????????????? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
597 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic mov pop push ldm stm movfpe movtpe mov.l ers,@erd l 4 mov.l ers,@(d:16,erd) l 6 mov.l ers,@(d:32,erd) l 10 mov.l ers,@-erd l 4 mov.l ers,@aa:16 l 6 mov.l ers,@aa:32 l 8 pop.w rn w 2 pop.l ern l 4 push.w rn w 2 push.l ern l 4 ldm @sp+,(erm-ern) l 4 stm (erm-ern),@-sp l 4 movfpe @aa:16,rd movtpe rs,@aa:16 ers32 ? @erd ? ? 0 ? 4 ers32 ? @(d:16,erd) ? ? 0 ? 5 ers32 ? @(d:32,erd) ? ? 0 ? 7 erd32-4 ? erd32,ers32 ? @ erd ?? 0 ? 5 ers32 ? @aa:16 ? ? 0 ? 5 ers32 ? @aa:32 ? ? 0 ? 6 @sp ? rn16,sp+2 ? sp ? ? 0 ? 3 @sp ? ern32,sp+4 ? sp ? ? 0 ? 5 sp-2 ? sp,rn16 ? @sp ? ? 0 ? 3 sp-4 ? sp,ern32 ? @sp ? ? 0 ? 5 (@sp ? ern32,sp+4 ? sp) ?????? 7/9/11 [1] repeated for each register restored (sp-4 ? sp,ern32 ? @sp) ?????? 7/9/11 [1] repeated for each register saved [2] [2] operation condition code normal ihnzvc advanced no. of states * 1 ?????????? ?????????? cannot be used in the h8s/2355 series cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
598 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic add addx adds inc daa sub add.b #xx:8,rd b 2 add.b rs,rd b 2 add.w #xx:16,rd w 4 add.w rs,rd w 2 add.l #xx:32,erd l 6 add.l ers,erd l 2 addx #xx:8,rd b 2 addx rs,rd b 2 adds #1,erd l 2 adds #2,erd l 2 adds #4,erd l 2 inc.b rd b 2 inc.w #1,rd w 2 inc.w #2,rd w 2 inc.l #1,erd l 2 inc.l #2,erd l 2 daa rd b 2 sub.b rs,rd b 2 sub.w #xx:16,rd w 4 rd8+#xx:8 ? rd8 ? 1 rd8+rs8 ? rd8 ? 1 rd16+#xx:16 ? rd16 ? [3] 2 rd16+rs16 ? rd16 ? [3] 1 erd32+#xx:32 ? erd32 ? [4] 3 erd32+ers32 ? erd32 ? [4] 1 rd8+#xx:8+c ? rd8 ? [5] 1 rd8+rs8+c ? rd8 ? [5] 1 erd32+1 ? erd32 ? ? ? ? ? ? 1 erd32+2 ? erd32 ? ? ? ? ? ? 1 erd32+4 ? erd32 ? ? ? ? ? ? 1 rd8+1 ? rd8 ? ? ? 1 rd16+1 ? rd16 ? ? ? 1 rd16+2 ? rd16 ? ? ? 1 erd32+1 ? erd32 ? ? ? 1 erd32+2 ? erd32 ? ? ? 1 rd8 decimal adjust ? rd8 ? ** 1 rd8-rs8 ? rd8 ? 1 rd16-#xx:16 ? rd16 ? [3] 2 operation condition code normal ihnzvc advanced no. of states * 1 ??? ? ???????? ?? ????? ???????? ???????? ???????? ?????? ???????? ?? ?? (2) arithmetic instructions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
599 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic sub subx subs dec das mulxu mulxs sub.w rs,rd w 2 sub.l #xx:32,erd l 6 sub.l ers,erd l 2 subx #xx:8,rd b 2 subx rs,rd b 2 subs #1,erd l 2 subs #2,erd l 2 subs #4,erd l 2 dec.b rd b 2 dec.w #1,rd w 2 dec.w #2,rd w 2 dec.l #1,erd l 2 dec.l #2,erd l 2 das rd b 2 mulxu.b rs,rd b 2 mulxu.w rs,erd w 2 mulxs.b rs,rd b 4 mulxs.w rs,erd w 4 rd16-rs16 ? rd16 ? [3] 1 erd32-#xx:32 ? erd32 ? [4] 3 erd32-ers32 ? erd32 ? [4] 1 rd8-#xx:8-c ? rd8 ? [5] 1 rd8-rs8-c ? rd8 ? [5] 1 erd32-1 ? erd32 ?????? 1 erd32-2 ? erd32 ?????? 1 erd32-4 ? erd32 ?????? 1 rd8-1 ? rd8 ? ? ? 1 rd16-1 ? rd16 ? ? ? 1 rd16-2 ? rd16 ? ? ? 1 erd32-1 ? erd32 ? ? ? 1 erd32-2 ? erd32 ? ? ? 1 rd8 decimal adjust ? rd8 ? * * ? rd8 rs8 ? rd16 (unsigned multiplication) ?????? 12 rd16 rs16 ? erd32 ?????? 20 (unsigned multiplication) rd8 rs8 ? rd16 (signed multiplication) ?? ?? 13 rd16 rs16 ? erd32 ? ? ? ? 21 (signed multiplication) operation condition code normal ihnzvc advanced no. of states * 1 ?? ?? ?????? ?????? ????? ??? ????? ????? ????? ?? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
600 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic divxu divxs cmp neg extu divxu.b rs,rd b 2 divxu.w rs,erd w 2 divxs.b rs,rd b 4 divxs.w rs,erd w 4 cmp.b #xx:8,rd b 2 cmp.b rs,rd b 2 cmp.w #xx:16,rd w 4 cmp.w rs,rd w 2 cmp.l #xx:32,erd l 6 cmp.l ers,erd l 2 neg.b rd b 2 neg.w rd w 2 neg.l erd l 2 extu.w rd w 2 extu.l erd l 2 rd16 rs8 ? rd16 (rdh: remainder, ? ? [6] [7] ? ? 12 rdl: quotient) (unsigned division) erd32 rs16 ? erd32 (ed: remainder, ? ? [6] [7] ? ? 20 rd: quotient) (unsigned division) rd16 rs8 ? rd16 (rdh: remainder, ? ? [8] [7] ? ? 13 rdl: quotient) (signed division) erd32 rs16 ? erd32 (ed: remainder, ? ? [8] [7] ? ? 21 rd: quotient) (signed division) rd8-#xx:8 ? 1 rd8-rs8 ? 1 rd16-#xx:16 ? [3] 2 rd16-rs16 ? [3] 1 erd32-#xx:32 ? [4] 3 erd32-ers32 ? [4] 1 0-rd8 ? rd8 ? 1 0-rd16 ? rd16 ? 1 0-erd32 ? erd32 ? 1 0 ? ( of rd16) ? ? 0 0 ? 1 0 ? ( of erd32) ? ? 0 0 ? 1 operation condition code normal ihnzvc advanced no. of states * 1 ??? ?? ??????????? ????????? ????????? ????????? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
601 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic exts tas mac clrmac ldmac stmac exts.w rd w 2 exts.l erd l 2 tas @erd b 4 mac @ern+, @erm+ clrmac ldmac ers,mach ldmac ers,macl stmac mach,erd stmac macl,erd ( of rd16) ? ?? 0 ? 1 ( of rd16) ( of erd32) ? ?? 0 ? 1 ( of erd32) @erd-0 ? ccr set, (1) ? ?? 0 ? 4 ( < bit 7 > of @erd) [2] operation condition code normal ihnzvc advanced no. of states * 1 ? ? ? ? ? ? cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
602 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic and or xor not and.b #xx:8,rd b 2 and.b rs,rd b 2 and.w #xx:16,rd w 4 and.w rs,rd w 2 and.l #xx:32,erd l 6 and.l ers,erd l 4 or.b #xx:8,rd b 2 or.b rs,rd b 2 or.w #xx:16,rd w 4 or.w rs,rd w 2 or.l #xx:32,erd l 6 or.l ers,erd l 4 xor.b #xx:8,rd b 2 xor.b rs,rd b 2 xor.w #xx:16,rd w 4 xor.w rs,rd w 2 xor.l #xx:32,erd l 6 xor.l ers,erd l 4 not.b rd b 2 not.w rd w 2 not.l erd l 2 rd8 #xx:8 ? rd8 ? ? 0 ? 1 rd8 rs8 ? rd8 ? ? 0 ? 1 rd16 #xx:16 ? rd16 ? ? 0 ? 2 rd16 rs16 ? rd16 ? ? 0 ? 1 erd32 #xx:32 ? erd32 ? ? 0 ? 3 erd32 ers32 ? erd32 ? ? 0 ? 2 rd8 #xx:8 ? rd8 ? ? 0 ? 1 rd8 rs8 ? rd8 ? ? 0 ? 1 rd16 #xx:16 ? rd16 ? ? 0 ? 2 rd16 rs16 ? rd16 ? ? 0 ? 1 erd32 #xx:32 ? erd32 ? ? 0 ? 3 erd32 ers32 ? erd32 ? ? 0 ? 2 rd8 ? #xx:8 ? rd8 ? ? 0 ? 1 rd8 ? rs8 ? rd8 ? ? 0 ? 1 rd16 ? #xx:16 ? rd16 ? ? 0 ? 2 rd16 ? rs16 ? rd16 ? ? 0 ? 1 erd32 ? #xx:32 ? erd32 ? ? 0 ? 3 erd32 ? ers32 ? erd32 ? ? 0 ? 2 a rd8 ? rd8 ? ? 0 ? 1 a rd16 ? rd16 ? ? 0 ? 1 a erd32 ? erd32 ? ? 0 ? 1 operation condition code normal ihnzvc advanced no. of states * 1 ????????????????????? ????????????????????? (3) logical instructions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
603 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic shal shar shll shal.b rd b 2 shal.b #2,rd b 2 shal.w rd w 2 shal.w #2,rd w 2 shal.l erd l 2 shal.l #2,erd l 2 shar.b rd b 2 shar.b #2,rd b 2 shar.w rd w 2 shar.w #2,rd w 2 shar.l erd l 2 shar.l #2,erd l 2 shll.b rd b 2 shll.b #2,rd b 2 shll.w rd w 2 shll.w #2,rd w 2 shll.l erd l 2 shll.l #2,erd l 2 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 operation condition code normal ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ?????? ?????????????????? c msb lsb msb lsb 0 c msb lsb c 0 (4) shift instructions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
604 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic shlr rotxl rotxr shlr.b rd b 2 shlr.b #2,rd b 2 shlr.w rd w 2 shlr.w #2,rd w 2 shlr.l erd l 2 shlr.l #2,erd l 2 rotxl.b rd b 2 rotxl.b #2,rd b 2 rotxl.w rd w 2 rotxl.w #2,rd w 2 rotxl.l erd l 2 rotxl.l #2,erd l 2 rotxr.b rd b 2 rotxr.b #2,rd b 2 rotxr.w rd w 2 rotxr.w #2,rd w 2 rotxr.l erd l 2 rotxr.l #2,erd l 2 001 001 001 001 001 001 01 01 01 01 01 01 01 01 01 01 01 01 operation condition code normal ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ???????????? c msb lsb 0 c msb lsb c msb lsb www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
605 0 1 0 1 0 1 0 1 0 1 0 1 01 01 01 0 1 01 101 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic rotl rotr rotl.b rd b 2 rotl.b #2,rd b 2 rotl.w rd w 2 rotl.w #2,rd w 2 rotl.l erd l 2 rotl.l #2,erd l 2 rotr.b rd b 2 rotr.b #2,rd b 2 rotr.w rd w 2 rotr.w #2,rd w 2 rotr.l erd l 2 rotr.l #2,erd l 2 operation condition code normal ihnzvc advanced no. of states * 1 ???????????? ???????????? ???????????? c msb lsb c msb lsb www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
606 (5) bit-manipulation instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bset bclr bset #xx:3,rd b 2 bset #xx:3,@erd b 4 bset #xx:3,@aa:8 b 4 bset #xx:3,@aa:16 b 6 bset #xx:3,@aa:32 b 8 bset rn,rd b 2 bset rn,@erd b 4 bset rn,@aa:8 b 4 bset rn,@aa:16 b 6 bset rn,@aa:32 b 8 bclr #xx:3,rd b 2 bclr #xx:3,@erd b 4 bclr #xx:3,@aa:8 b 4 bclr #xx:3,@aa:16 b 6 bclr #xx:3,@aa:32 b 8 bclr rn,rd b 2 bclr rn,@erd b 4 bclr rn,@aa:8 b 4 bclr rn,@aa:16 b 6 (#xx:3 of rd8) ? 1 ?????? 1 (#xx:3 of @erd) ? 1 ?????? 4 (#xx:3 of @aa:8) ? 1 ?????? 4 (#xx:3 of @aa:16) ? 1 ?????? 5 (#xx:3 of @aa:32) ? 1 ?????? 6 (rn8 of rd8) ? 1 ?????? 1 (rn8 of @erd) ? 1 ?????? 4 (rn8 of @aa:8) ? 1 ?????? 4 (rn8 of @aa:16) ? 1 ?????? 5 (rn8 of @aa:32) ? 1 ?????? 6 (#xx:3 of rd8) ? 0 ?????? 1 (#xx:3 of @erd) ? 0 ?????? 4 (#xx:3 of @aa:8) ? 0 ?????? 4 (#xx:3 of @aa:16) ? 0 ?????? 5 (#xx:3 of @aa:32) ? 0 ?????? 6 (rn8 of rd8) ? 0 ?????? 1 (rn8 of @erd) ? 0 ?????? 4 (rn8 of @aa:8) ? 0 ?????? 4 (rn8 of @aa:16) ? 0 ?????? 5 operation condition code normal ihnzvc advanced no. of states * 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
607 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bclr bnot btst bclr rn,@aa:32 b 8 bnot #xx:3,rd b 2 bnot #xx:3,@erd b 4 bnot #xx:3,@aa:8 b 4 bnot #xx:3,@aa:16 b 6 bnot #xx:3,@aa:32 b 8 bnot rn,rd b 2 bnot rn,@erd b 4 bnot rn,@aa:8 b 4 bnot rn,@aa:16 b 6 bnot rn,@aa:32 b 8 btst #xx:3,rd b 2 btst #xx:3,@erd b 4 btst #xx:3,@aa:8 b 4 btst #xx:3,@aa:16 b 6 (rn8 of @aa:32) ? 0 ?????? 6 (#xx:3 of rd8) ? [a (#xx:3 of rd8)] ?????? 1 (#xx:3 of @erd) ? ?????? 4 [a (#xx:3 of @erd)] (#xx:3 of @aa:8) ? ?????? 4 [a (#xx:3 of @aa:8)] (#xx:3 of @aa:16) ? ?????? 5 [a (#xx:3 of @aa:16)] (#xx:3 of @aa:32) ? ?????? 6 [a (#xx:3 of @aa:32)] (rn8 of rd8) ? [a (rn8 of rd8)] ?????? 1 (rn8 of @erd) ? [a (rn8 of @erd)] ?????? 4 (rn8 of @aa:8) ? [a (rn8 of @aa:8)] ?????? 4 (rn8 of @aa:16) ? ?????? 5 [a (rn8 of @aa:16)] (rn8 of @aa:32) ? ?????? 6 [a (rn8 of @aa:32)] a(#xx:3 of rd8) ? z ??? ?? 1 a(#xx:3 of @erd) ? z ??? ?? 3 a(#xx:3 of @aa:8) ? z ??? ?? 3 a(#xx:3 of @aa:16) ? z ??? ?? 4 operation condition code normal ihnzvc advanced no. of states * 1 ???? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
608 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic btst bld bild bst btst #xx:3,@aa:32 b 8 btst rn,rd b 2 btst rn,@erd b 4 btst rn,@aa:8 b 4 btst rn,@aa:16 b 6 btst rn,@aa:32 b 8 bld #xx:3,rd b 2 bld #xx:3,@erd b 4 bld #xx:3,@aa:8 b 4 bld #xx:3,@aa:16 b 6 bld #xx:3,@aa:32 b 8 bild #xx:3,rd b 2 bild #xx:3,@erd b 4 bild #xx:3,@aa:8 b 4 bild #xx:3,@aa:16 b 6 bild #xx:3,@aa:32 b 8 bst #xx:3,rd b 2 bst #xx:3,@erd b 4 bst #xx:3,@aa:8 b 4 ?#xx:3 of @aa:32) ? z ??? ?? 5 a(rn8 of rd8) ? z ??? ?? 1 a(rn8 of @erd) ? z ??? ?? 3 a(rn8 of @aa:8) ? z ??? ?? 3 a(rn8 of @aa:16) ? z ??? ?? 4 a(rn8 of @aa:32) ? z ??? ?? 5 (#xx:3 of rd8) ? c ????? 1 (#xx:3 of @erd) ? c ????? 3 (#xx:3 of @aa:8) ? c ????? 3 (#xx:3 of @aa:16) ? c ????? 4 (#xx:3 of @aa:32) ? c ????? 5 a (#xx:3 of rd8) ? c ????? 1 a (#xx:3 of @erd) ? c ????? 3 a (#xx:3 of @aa:8) ? c ????? 3 a (#xx:3 of @aa:16) ? c ????? 4 a (#xx:3 of @aa:32) ? c ????? 5 c ? (#xx:3 of rd8) ?????? 1 c ? (#xx:3 of @erd) ?????? 4 c ? (#xx:3 of @aa:8) ?????? 4 operation condition code normal ihnzvc advanced no. of states * 1 ?????????? ?????? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
609 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bst bist band biand bor bst #xx:3,@aa:16 b 6 bst #xx:3,@aa:32 b 8 bist #xx:3,rd b 2 bist #xx:3,@erd b 4 bist #xx:3,@aa:8 b 4 bist #xx:3,@aa:16 b 6 bist #xx:3,@aa:32 b 8 band #xx:3,rd b 2 band #xx:3,@erd b 4 band #xx:3,@aa:8 b 4 band #xx:3,@aa:16 b 6 band #xx:3,@aa:32 b 8 biand #xx:3,rd b 2 biand #xx:3,@erd b 4 biand #xx:3,@aa:8 b 4 biand #xx:3,@aa:16 b 6 biand #xx:3,@aa:32 b 8 bor #xx:3,rd b 2 bor #xx:3,@erd b 4 c ? (#xx:3 of @aa:16) ?????? 5 c ? (#xx:3 of @aa:32) ?????? 6 a c ? (#xx:3 of rd8) ?????? 1 a c ? (#xx:3 of @erd) ?????? 4 a c ? (#xx:3 of @aa:8) ?????? 4 a c ? (#xx:3 of @aa:16) ?????? 5 a c ? (#xx:3 of @aa:32) ?????? 6 c (#xx:3 of rd8) ? c ????? 1 c (#xx:3 of @erd) ? c ????? 3 c (#xx:3 of @aa:8) ? c ????? 3 c (#xx:3 of @aa:16) ? c ????? 4 c (#xx:3 of @aa:32) ? c ????? 5 c [a (#xx:3 of rd8)] ? c ????? 1 c [a (#xx:3 of @erd)] ? c ????? 3 c [a (#xx:3 of @aa:8)] ? c ????? 3 c [a (#xx:3 of @aa:16)] ? c ????? 4 c [a (#xx:3 of @aa:32)] ? c ????? 5 c (#xx:3 of rd8) ? c ????? 1 c (#xx:3 of @erd) ? c ????? 3 operation condition code normal ihnzvc advanced no. of states * 1 ???????????? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
610 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bor bior bxor bixor bor #xx:3,@aa:8 b 4 bor #xx:3,@aa:16 b 6 bor #xx:3,@aa:32 b 8 bior #xx:3,rd b 2 bior #xx:3,@erd b 4 bior #xx:3,@aa:8 b 4 bior #xx:3,@aa:16 b 6 bior #xx:3,@aa:32 b 8 bxor #xx:3,rd b 2 bxor #xx:3,@erd b 4 bxor #xx:3,@aa:8 b 4 bxor #xx:3,@aa:16 b 6 bxor #xx:3,@aa:32 b 8 bixor #xx:3,rd b 2 bixor #xx:3,@erd b 4 bixor #xx:3,@aa:8 b 4 bixor #xx:3,@aa:16 b 6 bixor #xx:3,@aa:32 b 8 c (#xx:3 of @aa:8) ? c ????? 3 c (#xx:3 of @aa:16) ? c ????? 4 c (#xx:3 of @aa:32) ? c ????? 5 c [a (#xx:3 of rd8)] ? c ????? 1 c [a (#xx:3 of @erd)] ? c ????? 3 c [a (#xx:3 of @aa:8)] ? c ????? 3 c [a (#xx:3 of @aa:16)] ? c ????? 4 c [a (#xx:3 of @aa:32)] ? c ????? 5 c ? (#xx:3 of rd8) ? c ????? 1 c ? (#xx:3 of @erd) ? c ????? 3 c ? (#xx:3 of @aa:8) ? c ????? 3 c ? (#xx:3 of @aa:16) ? c ????? 4 c ? (#xx:3 of @aa:32) ? c ????? 5 c ? [a (#xx:3 of rd8)] ? c ????? 1 c ? [a (#xx:3 of @erd)] ? c ????? 3 c ? [a (#xx:3 of @aa:8)] ? c ????? 3 c ? [a (#xx:3 of @aa:16)] ? c ????? 4 c ? [a (#xx:3 of @aa:32)] ? c ????? 5 operation condition code normal ihnzvc advanced no. of states * 1 ?????????????????? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
611 (6) branch instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bcc always 2 3 never 2 3 c z=0 ?????? 2 ?????? 3 c z=1 ?????? 2 ?????? 3 c=0 ?????? 2 ?????? 3 c=1 ?????? 2 ?????? 3 z=0 ?????? 2 ?????? 3 z=1 ?????? 2 ?????? 3 v=0 ?????? 2 ?????? 3 operation condition code branching condition normal ihnzvc advanced no. of states * 1 bra d:8(bt d:8) 2 if condition is true then bra d:16(bt d:16) 4 pc ? pc+d brn d:8(bf d:8) ? 2 else next; brn d:16(bf d:16) ? 4 bhi d:8 ? 2 bhi d:16 ? 4 bls d:8 ? 2 bls d:16 ? 4 bcc d:b(bhs d:8) ? 2 bcc d:16(bhs d:16) ? 4 bcs d:8(blo d:8) ? 2 bcs d:16(blo d:16) ? 4 bne d:8 ? 2 bne d:16 ? 4 beq d:8 ? 2 beq d:16 ? 4 bvc d:8 ? 2 bvc d:16 ? 4 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
612 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bcc v=1 2 3 n=0 2 3 n=1 2 3 n ? v=0 ?????? 2 ?????? 3 n ? v=1 ?????? 2 ?????? 3 z n ? v)=0 ?????? 2 ?????? 3 z (n ? v)=1 ?????? 2 ?????? 3 operation condition code branching condition normal ihnzvc advanced no. of states * 1 bvs d:8 2 bvs d:16 4 bpl d:8 2 bpl d:16 4 bmi d:8 2 bmi d:16 4 bge d:8 2 bge d:16 4 blt d:8 2 blt d:16 4 bgt d:8 2 bgt d:16 4 ble d:8 2 ble d:16 4 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
613 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic jmp bsr jsr rts jmp @ern 2 jmp @aa:24 4 jmp @@aa:8 2 bsr d:8 2 bsr d:16 4 jsr @ern 2 jsr @aa:24 4 jsr @@aa:8 2 rts 2 pc ? ern ?????? 2 pc ? aa:24 ?????? 3 pc ? @aa:8 ?????? 4 5 pc ? @-sp,pc ? pc+d:8 ?????? 3 4 pc ? @-sp,pc ? pc+d:16 ?????? 4 5 pc ? @-sp,pc ? ern ?????? 3 4 pc ? @-sp,pc ? aa:24 ?????? 4 5 pc ? @-sp,pc ? @aa:8 ?????? 4 6 pc ? @sp+ ?????? 4 5 operation condition code normal ihnzvc advanced no. of states * 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
614 (7) system control instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic trapa rte sleep ldc trapa #xx:2 rte sleep ldc #xx:8,ccr b 2 ldc #xx:8,exr b 4 ldc rs,ccr b 2 ldc rs,exr b 2 ldc @ers,ccr w 4 ldc @ers,exr w 4 ldc @(d:16,ers),ccr w 6 ldc @(d:16,ers),exr w 6 ldc @(d:32,ers),ccr w 10 ldc @(d:32,ers),exr w 10 ldc @ers+,ccr w 4 ldc @ers+,exr w 4 ldc @aa:16,ccr w 6 ldc @aa:16,exr w 6 ldc @aa:32,ccr w 8 ldc @aa:32,exr w 8 pc ? @-sp,ccr ? @-sp, 1 ????? 7 [9] 8 [9] exr ? @-sp, ? pc exr ? @sp+,ccr ? @sp+, 5 [9] pc ? @sp+ transition to power-down state ?????? 2 #xx:8 ? ccr 1 #xx:8 ? exr ?????? 2 rs8 ? ccr 1 rs8 ? exr ?????? 1 @ers ? ccr 3 @ers ? exr ?????? 3 @(d:16,ers) ? ccr 4 @(d:16,ers) ? exr ?????? 4 @(d:32,ers) ? ccr 6 @(d:32,ers) ? exr ?????? 6 @ers ? ccr,ers32+2 ? ers32 4 @ers ? exr,ers32+2 ? ers32 ?????? 4 @aa:16 ? ccr 4 @aa:16 ? exr ?????? 4 @aa:32 ? ccr 5 @aa:32 ? exr ?????? 5 operation condition code normal ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
615 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic stc andc orc xorc nop stc ccr,rd b 2 stc exr,rd b 2 stc ccr,@erd w 4 stc exr,@erd w 4 stc ccr,@(d:16,erd) w 6 stc exr,@(d:16,erd) w 6 stc ccr,@(d:32,erd) w 10 stc exr,@(d:32,erd) w 10 stc ccr,@-erd w 4 stc exr,@-erd w 4 stc ccr,@aa:16 w 6 stc exr,@aa:16 w 6 stc ccr,@aa:32 w 8 stc exr,@aa:32 w 8 andc #xx:8,ccr b 2 andc #xx:8,exr b 4 orc #xx:8,ccr b 2 orc #xx:8,exr b 4 xorc #xx:8,ccr b 2 xorc #xx:8,exr b 4 nop 2 ccr ? rd8 ?????? 1 exr ? rd8 ?????? 1 ccr ? @erd ?????? 3 exr ? @erd ?????? 3 ccr ? @(d:16,erd) ?????? 4 exr ? @(d:16,erd) ?????? 4 ccr ? @(d:32,erd) ?????? 6 exr ? @(d:32,erd) ?????? 6 erd32-2 ? erd32,ccr ? @erd ?????? 4 erd32-2 ? erd32,exr ? @erd ?????? 4 ccr ? @aa:16 ?????? 4 exr ? @aa:16 ?????? 4 ccr ? @aa:32 ?????? 5 exr ? @aa:32 ?????? 5 ccr #xx:8 ? ccr 1 exr #xx:8 ? exr ?????? 2 ccr #xx:8 ? ccr 1 exr #xx:8 ? exr ?????? 2 ccr ? #xx:8 ? ccr 1 exr ? #xx:8 ? exr ?????? 2 pc ? pc+2 ?????? 1 operation condition code normal ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
616 (8) block transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic eepmov notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located i n on-chip memory. 2. n is the initial value of r4l or r4. [1] seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] cannot be used in the h8s/2355 series. [3] set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] retains its previous value when the result is zero; otherwise cleared to 0. [6] set to 1 when the divisor is negative; otherwise cleared to 0. [7] set to 1 when the divisor is zero; otherwise cleared to 0. [8] set to 1 when the quotient is negative; otherwise cleared to 0. [9] one additional state is required for execution when exr is valid. eepmov.b 4 eepmov.w 4 if r4l 0 ?????? 4+2n * 2 repeat @er5 ? @er6 er5+1 ? er5 er6+1 ? er6 r4l-1 ? r4l until r4l=0 else next; if r4 0 ?????? 4+2n * 2 repeat @er5 ? @er6 er5+1 ? er5 er6+1 ? er6 r4-1 ? r4 until r4=0 else next; operation condition code normal ihnzvc advanced no. of states * 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
617 a.2 instruction codes table a-2 shows the instruction codes. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
618 table a-2 instruction codes add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd adds #1,erd adds #2,erd adds #4,erd addx #xx:8,rd addx rs,rd and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd andc #xx:8,ccr andc #xx:8,exr band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion add adds addx and andc band bcc b b w w l l l l l b b b b w w l l b b b b b b b 1 0 0 ers imm erd 0 0 0 0 0 0 erd erd erd erd erd erd ers imm imm 0 erd 0 imm 0 imm 0 0 0 8 0 7 0 7 0 0 0 0 9 0 e 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 rd 8 9 9 a a b b b rd e rd 6 9 6 a 1 6 1 6 c e a a 0 8 1 8 rd rd rd rd rd rd rd 0 1 rd 0 0 0 0 0 6 0 7 7 6 6 6 6 0 0 76 0 76 0 imm imm imm imm abs disp disp rs 1 rs 1 0 8 9 rs rs 6 rs 6 f 4 1 3 0 1 imm imm abs disp disp imm imm abs imm www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
619 bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bcc 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 a 8 b 8 c 8 d 8 e 8 f 8 2 3 4 5 6 7 8 9 a b c d e f disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
620 bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bclr biand bild bior b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 1 0 1 0 1 0 imm erd erd imm erd imm erd imm erd 0 1 1 1 imm imm imm imm 0 1 1 1 imm imm imm imm 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 2 d f a a 2 d f a a 6 c e a a 7 c e a a 4 c e a a 1 3 rn 1 3 1 3 1 3 1 3 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 0 0 7 7 6 6 7 7 7 7 7 7 2 2 2 2 6 6 7 7 4 4 rn rn 0 0 0 0 0 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs 0 0 1 1 1 1 1 1 imm imm imm imm imm imm imm imm www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
621 bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bist bixor bld bnot b b b b b b b b b b b b b b b b b b b b b b b b b 1 0 1 0 0 0 0 0 0 imm erd imm erd imm erd imm erd erd imm imm imm imm imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 1 1 0 0 0 0 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 d f a a 5 c e a a 7 c e a a 1 d f a a 1 d f a a 1 3 1 3 1 3 1 3 rn 1 3 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 8 8 rd 0 8 8 6 6 7 7 7 7 7 7 6 6 7 7 5 5 7 7 1 1 1 1 rn rn 0 0 0 0 0 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1rn 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
622 bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bsr d:8 bsr d:16 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bor bset bsr bst btst b b b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 0 0 0 0 0 0 0 imm erd imm erd erd imm erd imm erd erd abs abs abs disp abs abs imm imm imm imm imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 0 0 0 0 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 4 c e a a 0 d f a a 0 d f a a 5 c 7 d f a a 3 c e a a 3 c 1 3 1 3 rn 1 3 0 1 3 1 3 rn rd 0 0 0 rd 0 8 8 rd 0 8 8 0 rd 0 8 8 rd 0 0 0 rd 0 7 7 7 7 6 6 6 6 7 7 6 4 4 0 0 0 0 7 7 3 3 3 rn rn rn 0 0 0 0 0 0 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 abs abs abs disp abs abs abs abs abs abs abs www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
623 btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 clrmac cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd daa rd das rd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd divxs.b rs,rd divxs.w rs,erd divxu.b rs,rd divxu.w rs,erd eepmov.b eepmov.w mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion btst bxor clrmac cmp daa das dec divxs divxu eepmov b b b b b b b b b b w w l l b b b w w l l b w b w 0 0 1 imm erd ers 0 0 0 0 0 erd erd erd erd erd imm imm 0 erd 0 imm 0 imm 0 0 7 6 6 7 7 7 6 6 a 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 e a a 5 c e a a rd c 9 d a f f f a b b b b 1 1 1 3 b b 1 3 1 3 rs 2 rs 2 0 0 0 5 d 7 f d d rs rs 5 d 0 0 rd 0 0 0 rd rd rd rd rd rd rd rd 0 0 rd c 4 6 7 7 5 5 5 5 3 5 5 1 3 9 9 rn rs rs 8 8 0 0 0 rd f f 6 7 3 5 rn 0 0 6 7 3 5 rn 0 0 abs abs imm abs abs imm abs abs imm cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
624 exts.w rd exts.l erd extu.w rd extu.l erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd jmp @ern jmp @aa:24 jmp @@aa:8 jsr @ern jsr @aa:24 jsr @@aa:8 ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion exts extu inc jmp jsr ldc w l w l b w w l l b b b b w w w w w w w w w w 0 0 ern ern 0 0 0 0 erd erd erd erd ers ers ers ers ers ers ers ers 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 7 7 a b b b b 9 a b d e f 7 1 3 3 1 1 1 1 1 1 1 1 1 1 d f 5 7 0 5 d 7 f 4 0 1 4 4 4 4 4 4 4 4 4 4 rd rd rd rd rd 0 0 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 6 6 6 6 7 7 6 6 6 6 7 9 9 f f 8 8 d d b b 0 0 0 0 0 0 0 0 0 0 0 0 6 6 b b 2 2 0 0 abs abs abs abs imm imm disp disp disp disp disp disp www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
625 0 0 rd abs rs rd ldc @aa:32,ccr ldc @aa:32,exr ldm.l @sp+, (ern-ern+1) ldm.l @sp+, (ern-ern+2) ldm.l @sp+, (ern-ern+3) ldmac ers,mach ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa :16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion ldc ldm ldmac mac mov w w l l l l l b b b b b b b b b b b b b b b b w w w w w 0 0 0 0 1 1 0 1 0 0 0 ers ers ers ers erd erd erd erd ers ers ers 0 0 0 ern+1 ern+2 ern+3 0 0 0 0 0 f 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 1 1 1 1 1 rd c 8 e 8 c rd a a 8 e 8 c rs a a 9 d 9 f 8 4 4 1 2 3 rs 0 2 8 a 0 rs 0 1 0 0 0 rd rd rd 0 rd rd rd rs rs 0 rs rs rs rd rd rd rd 0 6 6 6 6 6 6 6 6 b b d d d a a b 2 2 7 7 7 2 a 2 imm abs abs disp abs disp abs imm disp abs abs abs abs disp disp disp cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
626 mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,rd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16 ,erd mov.l @aa:32 ,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) * mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 movfpe @aa:16,rd movtpe rs,@aa:16 mulxs.b rs,rd mulxs.w rs,erd mulxu.b rs,rd mulxu.w rs,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion mov movfpe movtpe mulxs mulxu w w w w w w w w w l l l l l l l l l l l l l l b b b w b w 0 1 1 0 1 1 ers erd erd erd erd ers 0 0 0 erd erd erd ers ers ers ers erd erd erd erd 0 0 0 0 0 0 0 0 0 0 0 erd erd erd erd erd ers ers ers ers ers erd 0 0 erd ers 0 0 0 0 1 1 0 1 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 d b b 9 f 8 d b b a f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 0 2 8 a 0 0 0 0 0 0 0 0 0 0 0 0 0 c c rs rs rd rd rd rs rs 0 rs rs rs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd 6 6 6 7 6 6 6 6 6 7 6 6 6 5 5 b 9 f 8 d b b 9 f 8 d b b 0 2 a 0 2 8 a rs rs rs 0 0 rd 6 6 b b 2 a abs disp abs abs abs imm disp abs disp abs disp abs abs disp disp cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
627 neg.b rd neg.w rd neg.l erd nop not.b rd not.w rd not.l erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd orc #xx:8,ccr orc #xx:8,exr pop.w rn pop.l ern push.w rn push.l ern rotl.b rd rotl.b #2, rd rotl.w rd rotl.w #2, rd rotl.l erd rotl.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion neg nop not or orc pop push rotl b w l b w l b b w w l l b b w l w l b b w w l l 0 0 0 0 0 erd erd erd erd erd 1 1 1 0 1 1 1 c 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 7 7 7 0 7 7 7 rd 4 9 4 a 1 4 1 d 1 d 1 2 2 2 2 2 2 8 9 b 0 0 1 3 rs 4 rs 4 f 4 7 0 f 0 8 c 9 d b f rd rd 0 rd rd rd rd rd 0 1 rn 0 rn 0 rd rd rd rd imm imm 6 0 6 6 4 4 d d ers 0 0 0 erd ern ern 0 7 f imm imm imm www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
628 rotr.b rd rotr.b #2, rd rotr.w rd rotr.w #2, rd rotr.l erd rotr.l #2, erd rotxl.b rd rotxl.b #2, rd rotxl.w rd rotxl.w #2, rd rotxl.l erd rotxl.l #2, erd rotxr.b rd rotxr.b #2, rd rotxr.w rd rotxr.w #2, rd rotxr.l erd rotxr.l #2, erd rte rts shal.b rd shal.b #2, rd shal.w rd shal.w #2, rd shal.l erd shal.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion rotr rotxl rotxr rte rts shal b b w w l l b b w w l l b b w w l l b b w w l l 0 0 0 0 0 0 0 0 erd erd erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 c 9 d b f rd rd rd rd rd rd rd rd rd rd rd rd 0 0 rd rd rd rd www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
629 shar.b rd shar.b #2, rd shar.w rd shar.w #2, rd shar.l erd shar.l #2, erd shll.b rd shll.b #2, rd shll.w rd shll.w #2, rd shll.l erd shll.l #2, erd shlr.b rd shlr.b #2, rd shlr.w rd shlr.w #2, rd shlr.l erd shlr.l #2, erd sleep stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion shar shll shlr sleep stc b b w w l l b b w w l l b b w w l l b b w w w w w w w w 0 0 0 0 0 0 erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 rd rd rd rd rd rd rd rd rd rd rd rd 0 rd rd 0 1 0 1 0 1 0 1 erd erd erd erd erd erd erd erd 1 1 1 1 0 0 1 1 6 6 6 6 7 7 6 6 9 9 f f 8 8 d d 0 0 0 0 0 0 0 0 6 6 b b a a 0 0 disp disp disp disp www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
630 stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 stm.l(ern-ern+1), @-sp stm.l (ern-ern+2), @-sp stm.l (ern-ern+3), @-sp stmac mach,erd stmac macl,erd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subs #1,erd subs #2,erd subs #4,erd subx #xx:8,rd subx rs,rd tas @erd trapa #x:2 xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion stc stm stmac sub subs subx tas trapa xor w w w w l l l l l b w w l l l l l b b b b b w w l l 1 00 ers imm 0 0 0 0 0 0 erd erd erd erd erd erd erd ers 0 0 0 0 ern ern ern erd 0 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 b 1 0 5 d 1 7 6 7 0 1 1 1 1 1 1 1 8 9 9 a a b b b rd e 1 7 rd 5 9 5 a 1 4 4 4 4 1 2 3 rs 3 rs 3 0 8 9 rs e rs 5 rs 5 f 0 1 0 1 0 0 0 rd rd rd rd 0 0 rd rd rd 0 6 6 6 6 6 6 6 7 6 b b b b d d d b 5 8 8 a a f f f 0 0 0 0 c abs abs abs abs imm imm imm imm imm imm cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
631 xorc #xx:8,ccr xorc #xx:8,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion xorc b b 0 0 5 1 4 1 0 5 imm imm note: bit 7 of the 4th byte of the mov.l ers, @(d:32,erd) instruction can be either 1 or 0. legend address register 32-bit register register field general register register field general register register field general register 000 001 111 er0 er1 er7 0000 0001 0111 1000 1001 1111 r0 r1 r7 e0 e1 e7 0000 0001 0111 1000 1001 1111 r0h r1h r7h r0l r1l r7l 16-bit register 8-bit register imm: abs: disp: rs, rd, rn: ers, erd, ern, erm: the register fields specify general registers as follows. immediate data (2, 3, 8, 16, or 32 bits) absolute address (8, 16, 24, or 32 bits) displacement (8, 16, or 32 bits) register field (4 bits specifying an 8-bit or 16-bit register. the symbols rs, rd, and rn correspond to operand symbols rs, rd, and rn.) register field (3 bits specifying an address register or 32-bit register. the symbols ers, erd, ern, and erm correspond to oper and symbols ers, erd, ern, and erm.) * www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
632 a.3 operation code map table a-3 shows the operation code map. instruction code 1st byte 2nd byte ah al bh bl instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. 0 nop bra mulxu bset ah note: * cannot be used in the h8s/2355 series. al 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 brn divxu bnot 2 bhi mulxu bclr 3 bls divxu btst stc stmac ldc ldmac 4 orc or bcc rts or bor bior 6 andc and bne rte and 5 xorc xor bcs bsr xor bxor bixor band biand 7 ldc beq trapa bst bist bld bild 8 bvc mov 9 bvs a bpl jmp b bmi eepmov c bge bsr d blt mov e addx subx bgt jsr f ble mov.b add addx cmp subx or xor and mov add sub mov mov cmp table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(3) table a-3 operation code map (1) ** www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
633 instruction code 1st byte 2nd byte ah al bh bl 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 6a 79 7a 0 mov inc adds daa dec subs das bra mov mov mov shll shlr rotxl rotxr not 1 ldm brn add add 2 bhi mov cmp cmp 3 stm not bls sub sub 4 shll shlr rotxl rotxr bcc movfpe * or or 5 inc extu dec bcs xor xor 6 mac bne and and 7 inc shll shlr rotxl rotxr extu dec beq ldc stc 8 sleep bvc mov adds shal shar rotl rotr neg subs 9 bvs a clrmac bpl mov b neg bmi add mov sub cmp c shal shar rotl rotr bge movtpe * d inc exts dec blt e tas bgt f inc shal shar rotl rotr exts dec ble bh ah al table a.3(3) table a.3(3) table a.3(3) table a.3(4) table a.3(4) table a-3 operation code map (2) * * note: * cannot be used in the h8s/2355 series. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
634 instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl r is the register specification field. aa is the absolute address specification. instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. notes: ah al bh bl ch cl 01c05 01d05 01f06 7cr06 * 1 7cr07 * 1 7dr06 * 1 7dr07 * 1 7eaa6 * 2 7eaa7 * 2 7faa6 * 2 7faa7 * 2 0 mulxs bset bset bset bset 1 divxs bnot bnot bnot bnot 2 mulxs bclr bclr bclr bclr 3 divxs btst btst btst btst 4 or 5 xor 6 and 789abcdef 1. 2. bor bior bxor bixor band biand bld bild bst bist bor bior bxor bixor band biand bld bild bst bist table a-3 operation code map (3) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
635 instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of fh is 0. instruction when most significant bit of fh is 1. 5th byte 6th byte eh el fh fl instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of hh is 0. instruction when most significant bit of hh is 1. note: * aa is the absolute address specification. 5th byte 6th byte eh el fh fl 7th byte 8th byte gh gl hh hl 6a10aaaa6 * 6a10aaaa7 * 6a18aaaa6 * 6a18aaaa7 * ahalbhblchcldhdleh el 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef 6a30aaaaaaaa6 * 6a30aaaaaaaa7 * 6a38aaaaaaaa6 * 6a38aaaaaaaa7 * ahalbhbl ... fhflgh gl 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef table a-3 operation code map (4) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
636 a.4 number of states required for instruction execution the tables in this section can be used to calculate the number of states required for instruction execution by the cpu. table a-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. table a-4 indicates the number of states required for each cycle. the number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. bset #0, @ffffc7:8 from table a-5: i = l = 2, j = k = m = n = 0 from table a-4: s i = 4, s l = 2 number of states required for execution = 2 4 + 2 2 = 12 2. jsr @@30 from table a-5: i = j = k = 2, l = m = n = 0 from table a-4: s i = s j = s k = 4 number of states required for execution = 2 4 + 2 4 + 2 4 = 24 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
637 table a-4 number of states per cycle access conditions on-chip supporting external device module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 2 4 6 + 2m 2 3 + m branch address read s j stack operation s k byte data access s l 2 2 3 + m word data access s m 4 4 6 + 2m internal operation s n 11 1 1111 legend m: number of wait states inserted into external device access www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
638 table a-5 number of cycles in instruction execution instruction fetch mnemonic instruction add adds addx and andc band bcc add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd adds #1/2/4,erd addx #xx:8,rd addx rs,rd and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd andc #xx:8,ccr andc #xx:8,exr band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 bra d:16 (bt d:16) brn d:16 (bf d:16) 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 branch address read stack operation byte data access word data access internal operation ijklmn www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
639 instruction fetch mnemonic instruction branch address read stack operation byte data access word data access internal operation ijklmn bcc bclr biand bild bior bhi d:16 bls d:16 bcc d:16 (bhs d:16) bcs d:16 (blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bior #xx:8,rd bior #xx:8,@erd bior #xx:8,@aa:8 bior #xx:8,@aa:16 bior #xx:8,@aa:32 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
640 bist bixor bld bnot bor bset bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 2 2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 instruction fetch mnemonic instruction branch address read stack operation byte data access word data access internal operation ijklmn www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
641 bsr bst btst bxor clrmac cmp daa das dec divxs divxu bsr d:8 bsr d:16 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 clrmac cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd daa rd das rd dec.b rd dec.w #1/2,rd dec.l #1/2,erd divxs.b rs,rd divxs.w rs,erd divxu.b rs,rd divxu.w rs,erd 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 1 2 1 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 19 11 19 normal advanced normal advanced instruction fetch mnemonic instruction branch address read stack operation byte data access word data access internal operation ijklmn cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
642 eepmov exts extu inc jmp jsr ldc ldm ldmac eepmov.b eepmov.w exts.w rd exts.l erd extu.w rd extu.l erd inc.b rd inc.w #1/2,rd inc.l #1/2,erd jmp @ern jmp @aa:24 jmp @@aa:8 jsr @ern jsr @aa:24 jsr @@aa:8 ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr ldc @aa:32,ccr ldc @aa:32,exr ldm.l @sp+, (ern-ern+1) ldm.l @sp+, (ern-ern+2) ldm.l @sp+, (ern-ern+3) ldmac ers,mach ldmac ers,macl 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 1 2 1 2 1 2 1 2 1 2 4 6 8 2n+2 * 2 2n+2 * 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 normal advanced normal advanced normal advanced normal advanced instruction fetch mnemonic instruction branch address read stack operation byte data access word data access internal operation ijklmn cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
643 mac mov mac @ern+,@erm+ mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa:16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,erd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16,erd mov.l @aa:32,erd mov.l ers,@erd mov.l ers,@(d:16,erd) 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 instruction fetch mnemonic instruction branch address read stack operation byte data access word data access internal operation ijklmn cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
644 mov movfpe movtpe mulxs mulxu neg nop not or orc pop push rotl rotr mov.l ers,@(d:32,erd) mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 movfpe @:aa:16,rd movtpe rs,@:aa:16 mulxs.b rs,rd mulxs.w rs,erd mulxu.b rs,rd mulxu.w rs,erd neg.b rd neg.w rd neg.l erd nop not.b rd not.w rd not.l erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd orc #xx:8,ccr orc #xx:8,exr pop.w rn pop.l ern push.w rn push.l ern rotl.b rd rotl.b #2,rd rotl.w rd rotl.w #2,rd rotl.l erd rotl.l #2,erd rotr.b rd rotr.b #2,rd rotr.w rd rotr.w #2,rd rotr.l erd rotr.l #2,erd 5 2 3 4 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 2 1 2 1 11 19 11 19 1 1 1 1 can not be used in the h8s/2355 series instruction fetch mnemonic instruction branch address read stack operation byte data access word data access internal operation ijklmn www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
645 rotxl rotxr rte rts shal shar shll shlr sleep rotxl.b rd rotxl.b #2,rd rotxl.w rd rotxl.w #2,rd rotxl.l erd rotxl.l #2,erd rotxr.b rd rotxr.b #2,rd rotxr.w rd rotxr.w #2,rd rotxr.l erd rotxr.l #2,erd rte rts shal.b rd shal.b #2,rd shal.w rd shal.w #2,rd shal.l erd shal.l #2,erd shar.b rd shar.b #2,rd shar.w rd shar.w #2,rd shar.l erd shar.l #2,erd shll.b rd shll.b #2,rd shll.w rd shll.w #2,rd shll.l erd shll.l #2,erd shlr.b rd shlr.b #2,rd shlr.w rd shlr.w #2,rd shlr.l erd shlr.l #2,erd sleep 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 / 3 1 2 1 1 1 1 normal advanced * 1 instruction fetch mnemonic instruction branch address read stack operation byte data access word data access internal operation ijklmn www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
646 stc stm stmac sub subs subx tas trapa xor xorc stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 stm.l (ern-ern+1),@-sp stm.l (ern-ern+2),@-sp stm.l (ern-ern+3),@-sp stmac mach,erd stmac macl,erd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subs #1/2/4,erd subx #xx:8,rd subx rs,rd tas @erd trapa #x:2 xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd xorc #xx:8,ccr xorc #xx:8,exr 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 1 2 1 3 1 1 1 1 2 2 2 1 1 2 1 3 2 1 2 1 2 4 6 8 2 / 3 1 2 / 3 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 normal advanced * * notes: 1. 2. 2 when exr is invalid, 3 when exr is valid. when n bytes of data are transferred. instruction fetch mnemonic instruction branch address read stack operation byte data access word data access internal operation ijklmn cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
647 a.5 bus states during instruction execution table a-6 indicates the types of cycles that occur during instruction execution by the cpu. see table a-4 for the number of states per cycle. how to read the table: instruction jmp@aa:24 r:w 2nd internal operation 1 state r:w ea 1 2345678 end of instruction order of execution read effective address (word-size read) no read or write read 2nd word of current instruction (word-size read) legend r:b byte-size read r:w word-size read w:b byte-size write w:w word-size write :m transfer of the bus is not performed immediately after this cycle 2nd address of 2nd word (3rd and 4th bytes) 3rd address of 3rd word (5th and 6th bytes) 4th address of 4th word (7th and 8th bytes) 5th address of 5th word (9th and 10th bytes) next address of next instruction ea effective address vec vector address figure a-1 shows timing waveforms for the address bus and the rd , hwr , and lwr signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
648 address bus rd hwr , lwr r:w 2nd fetching 2nd byte of instruction at jump address fetching 1nd byte of instruction at jump address fetching 4th byte of instruction fetching 3rd byte of instruction r:w ea high level internal operation figure a-1 address bus, rd , hwr , and lwr timing (8-bit bus, three-state access, no wait states) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
649 instruction add.b #xx:8,rd r:w next add.b rs,rd r:w next add.w #xx:16,rd r:w 2nd r:w next add.w rs,rd r:w next add.l #xx:32,erd r:w 2nd r:w 3rd r:w next add.l ers,erd r:w next adds #1/2/4,erd r:w next addx #xx:8,rd r:w next addx rs,rd r:w next and.b #xx:8,rd r:w next and.b rs,rd r:w next and.w #xx:16,rd r:w 2nd r:w next and.w rs,rd r:w next and.l #xx:32,erd r:w 2nd r:w 3rd r:w next and.l ers,erd r:w 2nd r:w next andc #xx:8,ccr r:w next andc #xx:8,exr r:w 2nd r:w next band #xx:3,rd r:w next band #xx:3,@erd r:w 2nd r:b ea r:w:m next band #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next band #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next band #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bra d:8 (bt d:8) r:w next r:w ea brn d:8 (bf d:8) r:w next r:w ea bhi d:8 r:w next r:w ea bls d:8 r:w next r:w ea bcc d:8 (bhs d:8) r:w next r:w ea bcs d:8 (blo d:8) r:w next r:w ea bne d:8 r:w next r:w ea beq d:8 r:w next r:w ea bvc d:8 r:w next r:w ea bvs d:8 r:w next r:w ea bpl d:8 r:w next r:w ea bmi d:8 r:w next r:w ea bge d:8 r:w next r:w ea blt d:8 r:w next r:w ea bgt d:8 r:w next r:w ea 1 234 56789 table a-6 instruction execution cycles www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
650 instruction ble d:8 r:w next r:w ea bra d:16 (bt d:16) r:w 2nd internal operation, r:w ea 1 state brn d:16 (bf d:16) r:w 2nd internal operation, r:w ea 1 state bhi d:16 r:w 2nd internal operation, r:w ea 1 state bls d:16 r:w 2nd internal operation, r:w ea 1 state bcc d:16 (bhs d:16) r:w 2nd internal operation, r:w ea 1 state bcs d:16 (blo d:16) r:w 2nd internal operation, r:w ea 1 state bne d:16 r:w 2nd internal operation, r:w ea 1 state beq d:16 r:w 2nd internal operation, r:w ea 1 state bvc d:16 r:w 2nd internal operation, r:w ea 1 state bvs d:16 r:w 2nd internal operation, r:w ea 1 state bpl d:16 r:w 2nd internal operation, r:w ea 1 state bmi d:16 r:w 2nd internal operation, r:w ea 1 state bge d:16 r:w 2nd internal operation, r:w ea 1 state blt d:16 r:w 2nd internal operation, r:w ea 1 state bgt d:16 r:w 2nd internal operation, r:w ea 1 state ble d:16 r:w 2nd internal operation, r:w ea 1 state bclr #xx:3,rd r:w next bclr #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea 1 234 56789 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
651 instruction bclr #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bclr rn,rd r:w next bclr rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea biand #xx:3,rd r:w next biand #xx:3,@erd r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next biand #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bild #xx:3,rd r:w next bild #xx:3,@erd r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bild #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bior #xx:3,rd r:w next bior #xx:3,@erd r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bior #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bist #xx:3,rd r:w next bist #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bixor #xx:3,rd r:w next bixor #xx:3,@erd r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bixor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bld #xx:3,rd r:w next bld #xx:3,@erd r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bld #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bnot #xx:3,rd r:w next 1 234 56789 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
652 instruction bnot #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bnot rn,rd r:w next bnot rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bor #xx:3,rd r:w next bor #xx:3,@erd r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bset #xx:3,rd r:w next bset #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bset rn,rd r:w next bset rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bsr d:8 r:w next r:w ea w:w stack r:w next r:w ea w:w :m stack (h) w:w stack (l) bsr d:16 r:w 2nd internal operation, r:w ea w:w stack 1 state r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state bst #xx:3,rd r:w next bst #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea btst #xx:3,rd r:w next btst #xx:3,@erd r:w 2nd r:b ea r:w:m next 1 234 56789 normal advanced normal advanced www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
653 instruction 1 234 56789 btst #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next btst rn,rd r:w next btst rn,@erd r:w 2nd r:b ea r:w:m next btst rn,@aa:8 r:w 2nd r:b ea r:w:m next btst rn,@aa:16 r:w 2nd r:w 3rd r:b ea r:w: next btst rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w: next bxor #xx:3,rd r:w next bxor #xx:3,@erd r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bxor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next clrmac cmp.b #xx:8,rd r:w next cmp.b rs,rd r:w next cmp.w #xx:16,rd r:w 2nd r:w next cmp.w rs,rd r:w next cmp.l #xx:32,erd r:w 2nd r:w 3rd r:w next cmp.l ers,erd r:w next daa rd r:w next das rd r:w next dec.b rd r:w next dec.w #1/2,rd r:w next dec.l #1/2,erd r:w next divxs.b rs,rd r:w 2nd r:w next internal operation, 11 states divxs.w rs,erd r:w 2nd r:w next internal operation, 19 states divxu.b rs,rd r:w next internal operation, 11 states divxu.w rs,erd r:w next internal operation, 19 states eepmov.b r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next eepmov.w r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next exts.w rd r:w next ? repeated n times * 2 ? exts.l erd r:w next extu.w rd r:w next extu.l erd r:w next inc.b rd r:w next cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
654 instruction inc.w #1/2,rd r:w next inc.l #1/2,erd r:w next jmp @ern r:w next r:w ea jmp @aa:24 r:w 2nd internal operation, r:w ea 1 state jmp @@aa:8 normal r:w next r:w aa:8 internal operation, r:w ea 1 state advanced r:w next r:w:m aa:8 r:w aa:8 internal operation, r:w ea 1 state jsr @ern normal r:w next r:w ea w:w stack advanced r:w next r:w ea w:w :m stack (h) w:w stack (l) jsr @aa:24 normal r:w 2nd internal operation, r:w ea w:w stack 1 state advanced r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state jsr @@aa:8 normal r:w next r:w aa:8 w:w stack r:w ea advanced r:w next r:w:m aa:8 r:w aa:8 w:w :m stack (h) w:w stack (l) r:w ea ldc #xx:8,ccr r:w next ldc #xx:8,exr r:w 2nd r:w next ldc rs,ccr r:w next ldc rs,exr r:w next ldc @ers,ccr r:w 2nd r:w next r:w ea ldc @ers,exr r:w 2nd r:w next r:w ea ldc @(d:16,ers),ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:16,ers),exr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:32,ers),ccr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @(d:32,ers),exr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @ers+,ccr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @ers+,exr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @aa:16,ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:16,exr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:32,ccr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldc @aa:32,exr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldm.l @sp+, r:w 2nd r:w:m next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 (ern?rn+1) 1 state 1 234 56789 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
655 instruction ldm.l @sp+,(ernCern+2) r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldm.l @sp+,(ern?rn+3) r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldmac ers,mach ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd r:w next mov.b rs,rd r:w next mov.b @ers,rd r:w next r:b ea mov.b @(d:16,ers),rd r:w 2nd r:w next r:b ea mov.b @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:b ea mov.b @ers+,rd r:w next internal operation, r:b ea 1 state mov.b @aa:8,rd r:w next r:b ea mov.b @aa:16,rd r:w 2nd r:w next r:b ea mov.b @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.b rs,@erd r:w next w:b ea mov.b rs,@(d:16,erd) r:w 2nd r:w next w:b ea mov.b rs,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:b ea mov.b rs,@?rd r:w next internal operation, w:b ea 1 state mov.b rs,@aa:8 r:w next w:b ea mov.b rs,@aa:16 r:w 2nd r:w next w:b ea mov.b rs,@aa:32 r:w 2nd r:w 3rd r:w next w:b ea mov.w #xx:16,rd r:w 2nd r:w next mov.w rs,rd r:w next mov.w @ers,rd r:w next r:w ea mov.w @(d:16,ers),rd r:w 2nd r:w next r:w ea mov.w @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:w ea mov.w @ers+, rd r:w next internal operation, r:w ea 1 state mov.w @aa:16,rd r:w 2nd r:w next r:w ea mov.w @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.w rs,@erd r:w next w:w ea 1 234 56789 cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
656 instruction 1 234 56789 mov.w rs,@(d:16,erd) r:w 2nd r:w next w:w ea mov.w rs,@(d:32,erd) r:w 2nd r:w 3rd r:e 4th r:w next w:w ea mov.w rs,@Cerd r:w next internal operation, w:w ea 1 state mov.w rs,@aa:16 r:w 2nd r:w next w:w ea mov.w rs,@aa:32 r:w 2nd r:w 3rd r:w next w:w ea mov.l #xx:32,erd r:w 2nd r:w 3rd r:w next mov.l ers,erd r:w next mov.l @ers,erd r:w 2nd r:w:m next r:w: ea r:w ea+2 mov.l @(d:16,ers),erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @(d:32,ers),erd r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next r:w:m ea r:w ea+2 mov.l @ers+,erd r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state mov.l @aa:16,erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @aa:32,erd r:w 2nd r:w:m 3rd r:w 4th r:w next r:w:m ea r:w ea+2 mov.l ers,@erd r:w 2nd r:w:m next w:w: ea w:w ea+2 mov.l ers,@(d:16,erd) r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@(d:32,erd) r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next w:w:m ea w:w ea+2 mov.l ers,@Cerd r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state mov.l ers,@aa:16 r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@aa:32 r:w 2nd r:w:m 3rd r:w 4th r:w next w:w:m ea w:w ea+2 movfpe @aa:16,rd movtpe rs,@aa:16 mulxs.b rs,rd r:w 2nd r:w next internal operation, 11 states mulxs.w rs,erd r:w 2nd r:w next internal operation, 19 states mulxu.b rs,rd r:w next internal operation, 11 states mulxu.w rs,erd r:w next internal operation, 19 states neg.b rd r:w next neg.w rd r:w next neg.l erd r:w next nop r:w next not.b rd r:w next not.w rd r:w next not.l erd r:w next or.b #xx:8,rd r:w next or.b rs,rd r:w next cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
657 instruction or.w #xx:16,rd r:w 2nd r:w next or.w rs,rd r:w next or.l #xx:32,erd r:w 2nd r:w 3rd r:w next or.l ers,erd r:w 2nd r:w next orc #xx:8,ccr r:w next orc #xx:8,exr r:w 2nd r:w next pop.w rn r:w next internal operation, r:w ea 1 state pop.l ern r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state push.w rn r:w next internal operation, w:w ea 1 state push.l ern r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state rotl.b rd r:w next rotl.b #2,rd r:w next rotl.w rd r:w next rotl.w #2,rd r:w next rotl.l erd r:w next rotl.l #2,erd r:w next rotr.b rd r:w next rotr.b #2,rd r:w next rotr.w rd r:w next rotr.w #2,rd r:w next rotr.l erd r:w next rotr.l #2,erd r:w next rotxl.b rd r:w next rotxl.b #2,rd r:w next rotxl.w rd r:w next rotxl.w #2,rd r:w next rotxl.l erd r:w next rotxl.l #2,erd r:w next rotxr.b rd r:w next rotxr.b #2,rd r:w next rotxr.w rd r:w next rotxr.w #2,rd r:w next rotxr.l erd r:w next 1 234 56789 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
658 instruction rotxr.l #2,erd r:w next rte r:w next r:w stack (exr) r:w stack (h) r:w stack (l) internal operation, r:w * 4 1 state rts r:w next r:w stack internal operation, r:w * 4 1 state r:w next r:w:m stack (h) r:w stack (l) internal operation, r:w * 4 1 state shal.b rd r:w next shal.b #2,rd r:w next shal.w rd r:w next shal.w #2,rd r:w next shal.l erd r:w next shal.l #2,erd r:w next shar.b rd r:w next shar.b #2,rd r:w next shar.w rd r:w next shar.w #2,rd r:w next shar.l erd r:w next shar.l #2,erd r:w next shll.b rd r:w next shll.b #2,rd r:w next shll.w rd r:w next shll.w #2,rd r:w next shll.l erd r:w next shll.l #2,erd r:w next shlr.b rd r:w next shlr.b #2,rd r:w next shlr.w rd r:w next shlr.w #2,rd r:w next shlr.l erd r:w next shlr.l #2,erd r:w next sleep r:w next internal operation:m stc ccr,rd r:w next stc exr,rd r:w next stc ccr,@erd r:w 2nd r:w next w:w ea stc exr,@erd r:w 2nd r:w next w:w ea stc ccr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea 1 234 56789 normal advanced www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
659 instruction stc exr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc exr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc ccr,@Cerd r:w 2nd r:w next internal operation, w:w ea 1 state stc exr,@Cerd r:w 2nd r:w next internal operation, w:w ea 1 state stc ccr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc exr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stc exr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stm.l(ernCern+1),@Csp r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ern?rn+2),@?p r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ern?rn+3),@?p r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stmac mach,erd stmac macl,erd sub.b rs,rd r:w next sub.w #xx:16,rd r:w 2nd r:w next sub.w rs,rd r:w next sub.l #xx:32,erd r:w 2nd r:w 3rd r:w next sub.l ers,erd r:w next subs #1/2/4,erd r:w next subx #xx:8,rd r:w next subx rs,rd r:w next tas @erd r:w 2nd r:w next r:b:m ea w:b ea trapa #x:2 r:w next internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w vec internal operation, r:w * 7 1 state 1 state r:w next internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 7 1 state 1 state xor.b #xx8,rd r:w next xor.b rs,rd r:w next xor.w #xx:16,rd r:w 2nd r:w next xor.w rs,rd r:w next xor.l #xx:32,erd r:w 2nd r:w 3rd r:w next 1 234 56789 normal advanced cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
660 instruction xor.l ers,erd r:w 2nd r:w next xorc #xx:8,ccr r:w next xorc #xx:8,exr r:w 2nd r:w next reset exception r:w vec internal operation, r:w * 5 handling 1 state r:w vec r:w vec+2 internal operation, r:w * 5 1 state interrupt exception r:w * 6 internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w vec internal operation, r:w * 7 handling 1 state 1 state r:w * 6 internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 7 1 state 1 state notes: 1. eas is the contents of er5. ead is the contents of er6. 2. eas is the contents of er5. ead is the contents of er6. both registers are incremented by 1 after execution of the instructio n. n is the initial value of r4l or r4. if n = 0, these bus cycles are not executed. 3. repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. start address after return. 5. start address of the program. 6. prefetch address, equal to two plus the pc value pushed onto the stack. in recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. start address of the interrupt-handling routine. 1 234 56789 normal advanced normal advanced www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
661 a.6 condition code modification this section indicates the effect of each cpu instruction on the condition code. the notation used in the table is defined below. m = 31 for longword operands 15 for word operands 7 for byte operands si di ri dn 0 1 * z' c' the i-th bit of the source operand the i-th bit of the destination operand the i-th bit of the result the specified bit in the destination operand not affected modified according to the result of the instruction (see definition) always cleared to 0 always set to 1 undetermined (no guaranteed value) z flag before instruction execution c flag before instruction execution www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
662 table a-7 condition code modification instruction h n z v c definition add h = smC4 dmC4 + dmC4 rme4 + smC4 rme4 n = rm z = rm rme1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm adds addx h = smC4 dmC4 + dmC4 rme4 + smC4 rme4 n = rm z = z' rm ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm and 0 n = rm z = rm rme1 ...... r0 andc stores the corresponding bits of the result. no flags change when the operand is exr. band c = c' dn bcc bclr biand c = c' dn bild c = dn bior c = c' + dn bist bixor c = c' dn + c' dn bld c = dn bnot bor c = c' + dn bset bsr bst btst z = dn bxor c = c' dn + c' dn clrmac cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
663 instruction h n z v c definition cmp h = smC4 dme4 + dme4 rmC4 + smC4 rmC4 n = rm z = rm rme1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm daa * * n = rm z = rm rme1 ...... r0 c: decimal arithmetic carry das * * n = rm z = rm rme1 ...... r0 c: decimal arithmetic borrow dec n = rm z = rm rme1 ...... r0 v = dm rm divxs n = sm dm + sm dm z = sm sme1 ...... s0 divxu n = sm z = sm sme1 ...... s0 eepmov exts 0 n = rm z = rm rme1 ...... r0 extu 0 0 z = rm rme1 ...... r0 inc n = rm z = rm rme1 ...... r0 v = dm rm jmp jsr ldc stores the corresponding bits of the result. no flags change when the operand is exr. ldm ldmac cannnot be used in the h8s/2355 series mac www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
664 instruction h n z v c definition mov 0 n = rm z = rm rme1 ...... r0 movfpe can not be used in the h8s/2355 series movtpe mulxs n = r2m z = r2m r2me1 ...... r0 mulxu neg h = dmC4 + rmC4 n = rm z = rm rme1 ...... r0 v = dm rm c = dm + rm nop not 0 n = rm z = rm rme1 ...... r0 or 0 n = rm z = rm rme1 ...... r0 orc stores the corresponding bits of the result. no flags change when the operand is exr. pop 0 n = rm z = rm rme1 ...... r0 push 0 n = rm z = rm rme1 ...... r0 rotl 0 n = rm z = rm rme1 ...... r0 c = dm (1-bit shift) or c = dmC1 (2-bit shift) rotr 0 n = rm z = rm rme1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
665 instruction h n z v c definition rotxl 0 n = rm z = rm rme1 ...... r0 c = dm (1-bit shift) or c = dmC1 (2-bit shift) rotxr 0 n = rm z = rm rme1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) rte stores the corresponding bits of the result. rts shal n = rm z = rm rme1 ...... r0 v = dm dmC1 + dm dme1 (1-bit shift) v = dm dmC1 dmC2 dm dme1 dme2 (2-bit shift) c = dm (1-bit shift) or c = dmC1 (2-bit shift) shar 0 n = rm z = rm rme1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) shll 0 n = rm z = rm rme1 ...... r0 c = dm (1-bit shift) or c = dmC1 (2-bit shift) shlr 0 0 n = rm z = rm rme1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) sleep stc stm stmac cannot be used in the h8s/2355 series www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
666 instruction h n z v c definition sub h = smC4 dme4 + dme4 rmC4 + smC4 rmC4 n = rm z = rm rme1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm subs subx h = smC4 dme4 + dme4 rmC4 + smC4 rmC4 n = rm z = z' rm ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm tas 0 n = dm z = dm dme1 ...... d0 trapa xor 0 n = rm z = rm rme1 ...... r0 xorc stores the corresponding bits of the result. no flags change when the operand is exr. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
667 appendix b internal i/o register b.1 addresses address (low) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width hf800 mra sm1 sm0 dm1 dm0 md1 md0 dts sz dtc 16/32 * 1 bit to sar hfbff mrb chne disel dar cra crb hfe80 tcr3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu3 16 bit hfe81 tmdr3 bfb bfa md3 md2 md1 md0 hfe82 tior3h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 hfe83 tior3l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 hfe84 tier3 ttge tciev tgied tgiec tgieb tgiea hfe85 tsr3 tcfv tgfd tgfc tgfb tgfa hfe86 tcnt3 hfe87 hfe88 tgr3a hfe89 hfe8a tgr3b hfe8b hfe8c tgr3c hfe8d hfe8e tgr3d hfe8f www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
668 address (low) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width hfe90 tcr4 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu4 16 bit hfe91 tmdr4 md3md2md1md0 hfe92 tior4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 hfe94 tier4 ttge tcieu tciev tgieb tgiea hfe95 tsr4 tcfd tcfu tcfv tgfb tgfa hfe96 tcnt4 hfe97 hfe98 tgr4a hfe99 hfe9a tgr4b hfe9b hfea0 tcr5 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu5 16 bit hfea1 tmdr5 md3md2md1md0 hfea2 tior5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 hfea4 tier5 ttge tcieu tciev tgieb tgiea hfea5 tsr5 tcfd tcfu tcfv tgfb tgfa hfea6 tcnt5 hfea7 hfea8 tgr5a hfea9 hfeaa tgr5b hfeab hfeb0 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr port 8 bit hfeb1 p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr hfeb2 p3ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr hfeb4 p5ddr p53ddr p52ddr p51ddr p50ddr hfeb5 p6ddr p67ddr p66ddr p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr hfeb9 paddr pa7ddr pa6ddr pa5ddr pa4ddr pa3ddr pa2ddr pa1ddr pa0ddr hfeba pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr hfebb pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr hfebc pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr hfebd peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr hfebe pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr hfebf pgddr pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
669 address (low) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width hfec4 ipra ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 interrupt 8 bit hfec5 iprb ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 controller hfec6 iprc ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfec7 iprd ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfec8 ipre ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfec9 iprf ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfeca iprg ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfecb iprh ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfecc ipri ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfecd iprj ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfece iprk ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 hfed0 abwcr abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus controller 8 bit hfed1 astcr ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 hfed2 wcrh w71 w70 w61 w60 w51 w50 w41 w40 hfed3 wcrl w31 w30 w21 w20 w11 w10 w01 w00 hfed4 bcrh icis1 icis0 brstrm brsts1 brsts0 hfed5 bcrl brle eae waite hff2c iscrh irq7scb irq7sca irq6scb irq6sca irq5scb irq5sca irq4scb irq4sca interrupt 8 bit hff2d iscrl irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca controller hff2e ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e hff2f isr irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f hff30 to hff35 dtcer dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 dtc 8 bit hff37 dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 hff38 sbycr ssby sts2 sts1 sts0 ope power-down mode 8 bit hff39 syscr intm1 intm0 nmieg rame mcu 8 bit hff3a sckcr pstop sck2 sck1 sck0 clock pulse generator 8 bit hff3b mdcr mds2 mds1 mds0 mcu 8 bit hff3c mstpcrh mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 power-down 8 bit hff3d mstpcrl mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 mode h'ff44 reserved reserved www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
670 address (low) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width hff50 port1 p17 p16 p15 p14 p13 p12 p11 p10 port 8 bit hff51 port2 p27 p26 p25 p24 p23 p22 p21 p20 hff52 port3 p35 p34 p33 p32 p31 p30 hff53 port4 p47 p46 p45 p44 p43 p42 p41 p40 hff54 port5 p53p52p51p50 hff55 port6 p67 p66 p65 p64 p63 p62 p61 p60 hff59 porta pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 hff5a portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 hff5b portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 hff5c portd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 hff5d porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 hff5e portf pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 hff5f portg pg4 pg3 pg2 pg1 pg0 hff60 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr hff61 p2dr p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr hff62 p3dr p35dr p34dr p33dr p32dr p31dr p30dr hff64 p5dr p53dr p52dr p51dr p50dr hff65 p6dr p67dr p66dr p65dr p64dr p63dr p62dr p61dr p60dr hff69 padr pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr hff6a pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr hff6b pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr hff6c pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr hff6d pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr hff6e pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr hff6f pgdr pg4dr pg3dr pg2dr pg1dr pg0dr hff70 papcr pa7pcr pa6pcr pa5pcr pa4pcr pa3pcr pa2pcr pa1pcr pa0pcr hff71 pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr hff72 pcpcr pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr hff73 pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr hff74 pepcr pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr hff76 p3odr p35odr p34odr p33odr p32odr p31odr p30odr hff77 paodr pa7odr pa6odr pa5odr pa4odr pa3odr pa2odr pa1odr pa0odr www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
671 address (low) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width hff78 smr0 c/ a / gm * 2 chr pe o/ e stop mp cks1 cks0 sci0, smart card 8 bit hff79 brr0 interface 0 hff7a scr0 tie rie te re mpie teie cke1 cke0 hff7b tdr0 hff7c ssr0 tdre rdrf orer fer/ ers * 3 per tend mpb mpbt hff7d rdr0 hff7e scmr0 sdir sinv smif hff80 smr1 c/ a / gm * 2 chr pe o/ e stop mp cks1 cks0 sci1, smart card 8 bit hff81 brr1 interface 1 hff82 scr1 tie rie te re mpie teie cke1 cke0 hff83 tdr1 hff84 ssr1 tdre rdrf orer fer/ ers * 3 per tend mpb mpbt hff85 rdr1 hff86 scmr1 sdir sinv smif hff88 smr2 c/ a / gm * 2 chr pe o/ e stop mp cks1 cks0 sci2, smart card 8 bit hff89 brr2 interface 2 hff8a scr2 tie rie te re mpie teie cke1 cke0 hff8b tdr2 hff8c ssr2 tdre rdrf orer fer/ ers * 3 per tend mpb mpbt hff8d rdr2 hff8e scmr2 sdir sinv smif h'ff90 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter 8 bit h'ff91 addral ad1 ad0 h'ff92 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff93 addrbl ad1 ad0 h"ff94 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff95 addrcl ad1 ad0 h'ff96 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff97 addrdl ad1 ad0 h'ff98 adcsr adf adie adst scan cks ch1 ch0 h'ff99 adcr trgs1 trgs0 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
672 address (low) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width hffa4 dadr0 * 4 d/a converter * 4 8 bit hffa5 dadr1 * 4 hffa6 dacr * 4 daoe1 daoe0 dae hffb0 tcr0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer 16 bit hffb1 tcr1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channel 0, 1 hffb2 tcsr0 cmfb cmfa ovf adte os3 os2 os1 os0 hffb3 tcsr1 cmfb cmfa ovf os3 os2 os1 os0 hffb4 tcora0 hffb5 tcora1 hffb6 tcorb0 hffb7 tcorb1 hffb8 tcnt0 hffb9 tcnt1 hffbc (read) tcsr ovf wt/ it tme cks2 cks1 cks0 wdt 16 bit hffbd (read) tcnt hffbf (read) rstcsr wovf rste rsts hffc0 tstr cst5 cst4 cst3 cst2 cst1 cst0 tpu 16 bit hffc1 tsyr sync5 sync4 sync3 sync2 sync1 sync0 hffd0 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu0 16 bit hffd1 tmdr0 bfb bfa md3 md2 md1 md0 hffd2 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 hffd3 tior0l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 hffd4 tier0 ttge tciev tgied tgiec tgieb tgiea hffd5 tsr0 tcfv tgfd tgfc tgfb tgfa hffd6 tcnt0 hffd7 hffd8 tgr0a hffd9 hffda tgr0b hffdb hffdc tgr0c hffdd hffde tgr0d hffdf www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
673 address (low) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width hffe0 tcr1 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu1 16 bit hffe1 tmdr1 md3md2md1md0 hffe2 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 hffe4 tier1 ttge tcieu tciev tgieb tgiea hffe5 tsr1 tcfd tcfu tcfv tgfb tgfa hffe6 tcnt1 hffe7 hffe8 tgr1a hffe9 hffea tgr1b hffeb hfff0 tcr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu2 16 bit hfff1 tmdr2 md3md2md1md0 hfff2 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 hfff4 tier2 ttge tcieu tciev tgieb tgiea hfff5 tsr2 tcfd tcfu tcfv tgfb tgfa hfff6 tcnt2 hfff7 hfff8 tgr2a hfff9 hfffa tgr2b hfffb notes: 1. located in on-chip ram. the bus width is 32 bits when the dtc accesses this area as register information, and 16 bits otherwise. 2. functions as c/ a for sci use, and as gm for smart card interface use. 3. functions as fer for sci use, and as ers for smart card interface use. 4. in the h8s/2393 these bits are reserved, as a d/a converter is not supported. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
674 b.2 functions mradtc mode register a h'f800h'fbff dtc 7 sm1 undefined 6 sm0 undefined 5 dm1 undefined 4 dm0 undefined 3 md1 undefined 0 sz undefined 2 md0 undefined 1 dts undefined bit initial value read/write : : : 0 1 source address mode 0 1 0 1 destination address mode 0 1 dtc mode 0 1 normal mode repeat mode block transfer mode 0 1 0 1 dtc data transfer size 0 1 byte-size transfer dtc transfer mode select 0 1 word-size transfer destination side is repeat area or block area source side is repeat area or block area dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) dar is decremented after a transfer (by -1 when sz = 0; by -2 when sz = 1) dar is fixed sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) sar is decremented after a transfer (by -1 when sz = 0; by -2 when sz = 1) sar is fixed www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
675 mrbdtc mode register b h'f800h'fbff dtc 7 chne undefined 6 disel undefined 5 undefined 4 undefined 3 undefined 0 undefined 2 undefined 1 undefined bit initial value read/write : : : dtc chain transfer enable 0 1 end of dtc data transfer dtc chain transfer dtc interrupt select reserved only 0 should be written to these bits 0 1 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 after a data transfer ends, the cpu interrupt is enabled sardtc source address register h'f800h'fbff dtc 23 bit initial value read/write : : : 22 21 20 19 43210 - - - - - - - - - - - - specifies transfer data source address unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dardtc destination address register h'f800h'fbff dtc 23 bit initial value read/write : : : 22 21 20 19 43210 - - - - - - - - - - - - specifies transfer data destination address unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
676 cradtc transfer count register a h'f800h'fbff dtc 15 bit initial value read/write : : : 14 13 12 11109876543210 crah cral specifies the number of dtc data transfers unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined crbdtc transfer count register b h'f800h'fbff dtc 15 14 13 12 11109876543210 specifies the number of dtc block data transfers bit initial value read/write : : : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
677 tcr3timer control register 3 h'fe80 tpu3 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value read/write : : : tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 counter clear 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input internal clock: counts on ?1024 internal clock: counts on ?256 internal clock: counts on ?4096 timer prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 notes: 1. 2. synchronous operation setting is performed by setting the sync bit in tsyr to 1. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
678 tmdr3timer mode register 3 h'fe81 tpu3 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : : 0 buffer operation b tgrb operates normally 0 buffer operation a tgra operates normally 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * notes: 1. 2. * : don? care md3 is a reserved bit. in a write, it should always be written with 0. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. tgra and tgrc used together for buffer operation 1 tgrb and tgrd used together for buffer operation 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
679 tior3htimer i/o control register 3h h'fe82 tpu3 0 1 tgr3b i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 tgr3a is output compare register tgr3a i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges * : don? care * : don? care 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write : : : tgr3a is input capture register initial output is 0 output output disabled initial output is 1 output capture input source is tioca3 pin capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down tgr3b is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr3b is input capture register initial output is 0 output output disabled initial output is 1 output capture input source is tiocb3 pin capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down note: 1. if bits tpsc2 to tpsc0 in tcr4 are set to b'000, and ?1 is used as the tcnt4 count clock, this setting will be invalid and input capture will not occur. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
680 tior3ltimer i/o control register 3l h'fe83 tpu3 0 1 tgr3d i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 tgr3c is output compare register trg3c i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled 0 output at compare match 1 output at compare match toggle output at compare match * : don? care * : don? care notes: note: when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w bit initial value read/write : : : initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges capture input source is tiocc3 pin tgr3c is input capture register capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down tgr3d is output compare register * 2 output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges capture input source is tiocd3 pin tgr3d is input capture register * 2 capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down * 1 1 2 when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and ?1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
681 tier3timer interrupt enable register 3 h'fe84 tpu3 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value read/write : : : 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled overflow interrupt enable tgr interrupt enable d tgr interrupt enable c tgr interrupt enable b 0 1 interrupt requests (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 0 1 0 1 interrupt requests (tgia) by tgfa bit enabled interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled interrupt requests (tgic) by tgfc bit disabled interrupt requests (tgic) by tgfc bit enabled interrupt requests (tgid) by tgfd bit disabled interrupt requests (tgid) by tgfd bit enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
682 tsr3timer status register 3 h'fe85 tpu3 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value read/write : : : note: * can only be written with 0 for flag clearing. 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 overflow flag 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) 0 [clearing condition] ?when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfd after reading tgfd = 1 input capture/output compare flag d 1 [setting condition] 0 [clearing condition] ?when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfc after reading tgfc = 1 input capture/output compare flag c 1 [setting condition] 0 [clearing condition] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 input capture/output compare flag b 1 [setting condition] 0 [clearing condition] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 [setting condition] ?when tcnt=tgra while tgra is function- ing as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register ?when tcnt = tgrc while tgrc is functioning as output compare register ?when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register ?when tcnt = tgrd while tgrd is functioning as output compare register ?when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
683 tcnt3timer counter 3 h'fe86 tpu3 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up-counter tgr3atimer general register 3a h'fe88 tpu3 tgr3btimer general register 3b h'fe8a tpu3 tgr3ctimer general register 3c h'fe8c tpu3 tgr3dtimer general register 3d h'fe8e tpu3 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
684 tcr4timer control register 4 h'fe90 tpu4 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 0 1 0 1 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkc pin input internal clock: counts on ?1024 counts on tcnt5 overflow/underflow timer prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value read/write : : : note: this setting is ignored when channel 4 is in phase counting mode. note: * synchronous operating setting is performed by setting the sync bit tsyr to 1. note: this setting is ignored when channel 4 is in phase counting mode. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
685 tmdr4timer mode register 4 h'fe91 tpu4 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * notes: * : don? care 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : : md3 is a reserved bit. in a write, it should always be written with 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
686 tior4timer i/o control register 4 h'fe92 tpu4 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write : : : 0 1 tgr4b is output compare register tgr4b i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * tgr4a i/o control * : don? care 0 1 tgr4a is output compare register 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled 0 output at compare match 1 output at compare match toggle output at compare match * : don? care initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges tgr4a is input capture register capture input source is tioca4 pin input capture at generation of tgr3a compare match/input capture capture input source is tgr3a compare match/ input capture output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges tgr4b is input capture register capture input source is tiocb4 pin input capture at generation of tgr3c compare match/input capture capture input source is tgr3c compare match/ input capture www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
687 tier4timer interrupt enable register 4 h'fe94 tpu4 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value read/write : : : 0 1 0 1 0 1 interrupt requests (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 0 1 interrupt requests (tgia) by tgfa bit enabled interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled tgr interrupt enable b interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled overflow interrupt enable underflow interrupt enable interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled a/d conversion start request enable a/d conversion start request generation disabled a/d conversion start request generation enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
688 tsr4timer status register 4 h'fe95 tpu4 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value read/write : : : 0 1 tcnt counts down tcnt counts up count direction flag 0 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 underflow flag 1 [setting conditions] when the tcnt value underflows (changes from h'0000 to h'ffff) 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 overflow flag 1 [setting conditions] when the tcnt value overflows (changes from h'ffff to h'0000 ) 0 input capture/output compare flag b 1 0 [clearing condition] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 [setting conditions] note: * can only be written with 0 for fla g clearin g . ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing condition] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
689 tcnt4timer counter 4 h'fe96 tpu4 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. up/down-counter * tgr4atimer general register 4a h'fe98 tpu4 tgr4btimer general register 4b h'fe9a tpu4 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
690 tcr5timer control register 5 h'fea0 tpu5 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 0 1 0 1 internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkc pin input internal clock: counts on ?256 external clock: counts on tclkd pin input time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value read/write : : : note: 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges this setting is ignored when channel 5 is in phase counting mode. note: * synchronous operating setting is performed by setting the sync bit tsyr to 1. note: this setting is ignored when channel 5 is in phase counting mode. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
691 tmdr5timer mode register 5 h'fea1 tpu5 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * notes: md3 is a reserved bit. in a write, it should always be written with 0. * : don? care 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
692 tior5timer i/o control register 5 h'fea2 tpu5 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write : : : 0 1 tgr5b i/o control 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 tgr5a is output compare register tgr5a i/o control 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * output disabled 0 output at compare match 1 output at compare match toggle output at compare match * : don? care tgr5a is input capture register initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges capture input source is tioca5 pin tgr5b is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match * : don? care tgr5b is input capture register initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges capture input source is tiocb5 pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
693 tier5timer interrupt enable register 5 h'fea4 tpu5 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value read/write : : : 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled underflow interrupt enable tgr interrupt enable b 0 1 interrupt requests (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 0 1 overflow interrupt enable interrupt requests (tgia) by tgfa bit enabled interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
694 tsr5timer status register 5 h'fea5 tpu5 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value read/write : : : 0 1 tcnt counts down tcnt counts up count direction flag 0 underflow flag 1 0 overflow flag 1 0 input capture/output compare flag b 1 0 [clearing condition] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register note: * can only be written with 0 for flag clearing. [clearing condition] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting conditions] when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting conditions] when the tcnt value underflows (changes from h'0000 to h'ffff) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
695 tcnt5timer counter 5 h'fea6 tpu5 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. up/down-counter * tgr5atimer general register 5a h'fea8 tpu5 tgr5btimer general register 5b h'feaa tpu5 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w p1ddrport 1 data direction register h'feb0 port 1 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value read/write : : : specif y input or output for individual port 1 pins www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
696 p2ddrport 2 data direction register h'feb1 port 2 7 p27ddr 0 w 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 0 p20ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w specif y input or output for individual port 2 pins bit initial value read/write : : : p3ddrport 3 data direction register h'feb2 port 3 7 undefined 6 undefined 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w specif y input or output for individual port 3 pins bit initial value read/write : : : p5ddrport 5 data direction register h'feb4 port 5 7 undefined 6 undefined 5 undefined 4 undefined 3 p53ddr 0 w 0 p50ddr 0 w 2 p52ddr 0 w 1 p51ddr 0 w specify input or output for individual port 5 pins bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
697 p6ddrport 6 data direction register h'feb5 port 6 7 p67ddr 0 w 6 p66ddr 0 w 5 p65ddr 0 w 4 p64ddr 0 w 3 p63ddr 0 w 0 p60ddr 0 w 2 p62ddr 0 w 1 p61ddr 0 w specify input or output for individual port 6 pins bit initial value read/write : : : paddrport a data direction register h'feb9 port a 7 pa7ddr 0 w 6 pa6ddr 0 w 5 pa5ddr 0 w 4 pa4ddr 0 w 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit initial value read/write : : : specif y input or output for individual port a pins pbddrport b data direction register h'feba port b 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w specif y input or output for individual port b pins bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
698 pcddrport c data direction register h'febb port c 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w specif y input or output for individual port c pins bit initial value read/write : : : pdddrport d data direction register h'febc port d 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit initial value read/write : : : specify input or output for individual port d pins peddrport e data direction register h'febd port e 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w specif y input or output for individual port e pins bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
699 pfddrport f data direction register h'febe port f 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w specif y input or output for individual port f pins bit modes 1, 2, 4 to 6 initial value read/write modes 3, 7 initial value read/write : : : : : pgddrport g data direction register h'febf port g 7 undefined undefined 6 undefined undefined 5 undefined undefined 4 pg4ddr 1 w 0 w 3 pg3ddr 0 w 0 w 0 pg0ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w specif y input or output for individual port g pins bit modes 1, 4, 5 initial value read/write modes 2, 3, 6, 7 initial value read/write : : : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
700 ipra interrupt priority register a h'fec4 interrupt controller iprb interrupt priority register b h'fec5 interrupt controller iprc interrupt priority register c h'fec6 interrupt controller iprd interrupt priority register d h'fec7 interrupt controller ipre interrupt priority register e h'fec8 interrupt controller iprf interrupt priority register f h'fec9 interrupt controller iprg interrupt priority register g h'feca interrupt controller iprh interrupt priority register h h'fecb interrupt controller ipri interrupt priority register i h'fecc interrupt controller iprj interrupt priority register j h'fecd interrupt controller iprk interrupt priority register k h'fece interrupt controller 7 0 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 0 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w set priority (levels 7 to 0) for interrupt sources ipra iprb iprc iprd ipre iprf iprg iprh ipri iprj iprk register bits irq0 irq2 irq3 irq6 irq7 wdt * tpu channel 0 tpu channel 2 tpu channel 4 8-bit timer channel 0 * sci channel 1 irq1 irq4 irq5 dtc * a/d converter tpu channel 1 tpu channel 3 tpu channel 5 8-bit timer channel 1 sci channel 0 sci channel 2 6 to 4 2 to 0 correspondence between interrupt sources and ipr settings note: * reserved bits. these bits cannot be modified and are alwa y s read as 1. bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
701 abwcrbus width control register h'fed0 bus controller 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit modes 1 to 3, 5 to 7 initial value r/w mode 4 initial value read/write : : : : : area 7 to 0 bus width control 0 1 area n is designated for 16-bit access area n is designated for 8-bit access ( n = 7 to 0 ) astcraccess state control register h'fed1 bus controller 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value read/write : : : area 7 to 0 access state control 0 1 area n is designated for 2-state access wait state insertion in area n external space is disabled area n is designated for 3-state access wait state insertion in area n external space is enabled (n = 7 to 0) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
702 wcrhwait control register h h'fed2 bus controller 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value read/write : : : area 7 wait control area 6 wait control area 5 wait control area 4 wait control 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
703 wcrlwait control register l h'fed3 bus controller 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value read/write : : : area 3 wait control area 2 wait control area 1 wait control area 0 wait control 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
704 bcrhbus control register h h'fed4 bus controller 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write : : : idle cycle insert 1 0 1 idle cycle not inserted in case of successive external read cycles in different areas idle cycle inserted in case of successive external read cycles in different areas idle cycle insert 0 0 1 idle cycle not inserted in case of successive external read and external write cycles idle cycle inserted in case of successive external read and external write cycles area 0 burst rom enable 0 1 area 0 is basic bus interface area 0 is burst rom interface burst cycle select 1 0 1 burst cycle comprises 1 state burst cycle comprises 2 states burst cycle select 0 reserved only 0 should be written to these bits 0 1 max. 4 words in burst access max. 8 words in burst access www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
705 bcrlbus control register l h'fed5 bus controller 7 brle 0 r/w 6 0 r/w 5 eae 1 r/w 4 1 r/w 3 1 r/w 0 waite 0 r/w 2 1 r/w 1 0 r/w bit initial value read/write : : : bus release enable 0 1 external bus release is disabled external bus release is enabled wait pin enable reserved only 0 should be written to this bit reserved only 0 should be written to this bit reserved only 1 should be written to these bits 0 1 wait input by wait pin disabled wait input by wait pin enabled external addresses h'010000 to h'01ffff enable 0 1 notes: * do not access a reserved area. on-chip rom (h8s/2355) or reserved area * (h8s/2353) external addresses (in external expansion mode) or reserved area (in single-chip mode) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
706 iscrh irq sense control register h h'ff2c interrupt controller iscrl irq sense control register l h'ff2d interrupt controller 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value read/write : : : iscrh 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w irq7 to irq4 sense control irq3 to irq0 sense control 0 1 0 1 0 1 irqn input low level falling edge of irqn input rising edge of irqn input both falling and rising edges of irqn input irqnscb irqnsca interrupt request generation (n = 7 to 0) bit initial value read/write : : : iscrl www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
707 ierirq enable register h'ff2e interrupt controller 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w irqn enable 0 1 irqn interrupt disabled irqn interrupt enabled (n = 7 to 0) bit initial value read/write : : : isrirq status register h'ff2f interrupt controller 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value read/write note: * can only be written with 0 for flag clearing. : : : indicate the status of irq7 to irq0 interrupt requests www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
708 dtcera to dtcerfdtc enable registers h'ff30 to h'ff35 dtc 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w dtc activation enable bit initial value read/write : : : dtc activation by this interrupt is disabled [clearing conditions] ?when the disel bit is 1 and data transfer has ended ?hen the specified number of transfers have ended 0 1 dtc activation by this interrupt is enabled [holding condition] when the disel bit is 0 and the specified number of transfers have not ended correspondence between interrupt sources and dtcer bits register 76543210 dtcera irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 dtcerb adi tgi0a tgi0b tgi0c tgi0d tgi1a tgi1b dtcerc tgi2a tgi2b tgi3a tgi3b tgi3c tgi3d tgi4a tgi4b dtcerd tgi5a tgi5b cmia0 cmib0 cmia1 cmib1 dtcere rxi0 txi0 rxi1 txi1 dtcerf rxi2 txi2 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
709 dtvecrdtc vector register h'ff37 dtc 7 swdte 0 r/(w) * 6 dtvec6 0 r/w 5 dtvec5 0 r/w 4 dtvec4 0 r/w 3 dtvec3 0 r/w 0 dtvec0 0 r/w 2 dtvec2 0 r/w 1 dtvec1 0 r/w a value of 1 can always be written to the swdte bit, but 0 can only be written after 1 is read. note: * dtc software activation enable 0 1 dtc software activation is disabled [clearing condition] when the disel bit is 0 and the specified number of transfers have not ended dtc software activation is enabled [holding conditions] ? when the disel bit is 1 and data transfer has ended ? when the specified number of transfers have ended ? during data transfer due to software activation sets vector number for dtc software activation bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
710 sbycrstandby control register h'ff38 power-down state 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 0 r/w 2 0 1 0 software standby 0 1 transition to sleep mode after execution of sleep instruction transition to software standby mode after execution of sleep instruction standby timer select 0 1 0 1 0 1 0 1 0 1 0 1 0 1 standby time = 8192 states standby time = 16384 states standby time = 32768 states standby time = 65536 states standby time = 131072 states standby time = 262144 states reserved standby time = 16 states output port enable reserved only 0 should be written to this bit 0 1 in software standby mode, address bus and bus control signals are high-impedance bit initial value read/write : : : in software standby mode, address bus and bus control signals retain output state www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
711 syscrsystem control register h'ff39 mcu 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 0 1 0 r/w bit initial value read/write : : : interrupt control mode selection 0 1 0 1 0 1 interrupt control mode 0 interrupt control mode 2 nmi input edge select 0 1 falling edge rising edge ram enable reserved only 0 should be written to this bit reserved onl y 0 should be written to this bit 0 1 on-chip ram disabled on-chip ram enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
712 sckcrsystem clock control register h'ff3a clock pulse generator 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w 0 1 pstop normal operation ?output fixed high high impedance high impedance fixed high fixed high ?clock output control bus master clock select 0 1 0 1 0 1 0 1 0 1 0 1 bus master is in high-speed mode medium-speed clock is ?2 medium-speed clock is ?4 medium-speed clock is ?8 medium-speed clock is ?16 medium-speed clock is ?32 ?output fixed high sleep mode bit initial value read/write : : : software standby mode hardware standby mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
713 mdcrmode control register h'ff3b mcu 7 1 6 0 5 0 4 0 3 0 0 mds0 * r 2 mds2 * r 1 mds1 * r current mode pin operating mode bit initial value read/write : : : note: * determined by pins md 2 to md 0 mstpcrh module stop control register h h'ff3c power-down state mstpcrl module stop control register l h'ff3d power-down state 15 0 r/w 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl specifies module stop mode 0 1 module stop mode cleared module stop mode set bit initial value read/write : : : reserved register h'ff 7 0 6 0 5 0 r/w 4 0 3 0 0 0 2 0 1 0 bit initial value read/write : : : reserved only 0 should be written to these bits www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
714 port1port 1 register h'ff50 port 1 7 p17 * r 6 p16 * r 5 p15 * r 4 p14 * r 3 p13 * r 0 p10 * r 2 p12 * r 1 p11 * r note: * determined by the state of pins p1 7 to p1 0 . state of port 1 pins bit initial value read/write : : : port2port 2 register h'ff51 port 2 7 p27 * r 6 p26 * r 5 p25 * r 4 p24 * r 3 p23 * r 0 p20 * r 2 p22 * r 1 p21 * r state of port 2 pins note: * determined by the state of pins p2 7 to p2 0 . bit initial value read/write : : : port3port 3 register h'ff52 port 3 7 undefined 6 undefined 5 p35 * r 4 p34 * r 3 p33 * r 0 p30 * r 2 p32 * r 1 p31 * r state of port 3 pins note: * determined by the state of pins p3 5 to p3 0 . bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
715 port4port 4 register h'ff53 port 4 7 p47 * r 6 p46 * r 5 p45 * r 4 p44 * r 3 p43 * r 0 p40 * r 2 p42 * r 1 p41 * r state of port 4 pins note: * determined by the state of pins p4 7 to p4 0 . bit initial value read/write : : : port5port 5 register h'ff54 port 5 7 undefined 6 undefined 5 undefined 4 undefined 3 p53 * r 0 p50 * r 2 p52 * r 1 p51 * r state of port 5 pins note: * determined by the state of pins p5 3 to p5 0 . bit initial value read/write : : : port6port 6 register h'ff55 port 6 7 p67 * r 6 p66 * r 5 p65 * r 4 p64 * r 3 p63 * r 0 p60 * r 2 p62 * r 1 p61 * r state of port 6 pins note: * determined by the state of pins p6 7 to p6 0 . bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
716 portaport a register h'ff59 port a 7 pa7 * r 6 pa6 * r 5 pa5 * r 4 pa4 * r 3 pa3 * r 0 pa0 * r 2 pa2 * r 1 pa1 * r state of port a pins note: * determined by the state of pins pa 7 to pa 0 . bit initial value read/write : : : portbport b register h'ff5a port b 7 pb7 * r 6 pb6 * r 5 pb5 * r 4 pb4 * r 3 pb3 * r 0 pb0 * r 2 pb2 * r 1 pb1 * r state of port b pins note: * determined by the state of pins pb 7 to pb 0 . bit initial value read/write : : : portcport c register h'ff5b port c 7 pc7 * r 6 pc6 * r 5 pc5 * r 4 pc4 * r 3 pc3 * r 0 pc0 * r 2 pc2 * r 1 pc1 * r state of port c pins note: * determined by the state of pins pc 7 to pc 0 . bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
717 portdport d register h'ff5c port d 7 pd7 * r 6 pd6 * r 5 pd5 * r 4 pd4 * r 3 pd3 * r 0 pd0 * r 2 pd2 * r 1 pd1 * r state of port d pins note: * determined by the state of pins pd 7 to pd 0 . bit initial value read/write : : : porteport e register h'ff5d port e 7 pe7 * r 6 pe6 * r 5 pe5 * r 4 pe4 * r 3 pe3 * r 0 pe0 * r 2 pe2 * r 1 pe1 * r state of port e pins note: * determined by the state of pins pe 7 to pe 0 . bit initial value read/write : : : portfport f register h'ff5e port f 7 pf7 * r 6 pf6 * r 5 pf5 * r 4 pf4 * r 3 pf3 * r 0 pf0 * r 2 pf2 * r 1 pf1 * r state of port f pins note: * determined by the state of pins pf 7 to pf 0 . bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
718 portgport g register h'ff5f port g 7 undefined 6 undefined 5 undefined 4 pg4 * r 3 pg3 * r 0 pg0 * r 2 pg2 * r 1 pg1 * r state of port g pins note: * determined by the state of pins pg 4 to pg 0 . bit initial value read/write : : : p1drport 1 data register h'ff60 port 1 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w stores output data for port 1 pins (p1 7 to p1 0 ) bit initial value read/write : : : p2drport 2 data register h'ff61 port 2 7 p27dr 0 r/w 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 0 p20dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w stores output data for port 2 pins (p2 7 to p2 0 ) bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
719 p3drport 3 data register h'ff62 port 3 7 undefined 6 undefined 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w stores output data for port 3 pins (p3 5 to p3 0 ) bit initial value read/write : : : p5drport 5 data register h'ff64 port 5 7 undefined 6 undefined 5 undefined 4 undefined 3 p53dr 0 r/w 0 p50dr 0 r/w 2 p52dr 0 r/w 1 p51dr 0 r/w stores output data for port 5 pins (p5 3 to p5 0 ) bit initial value read/write : : : p6drport 6 data register h'ff65 port 6 7 p67dr 0 r/w 6 p66dr 0 r/w 5 p65dr 0 r/w 4 p64dr 0 r/w 3 p63dr 0 r/w 0 p60dr 0 r/w 2 p62dr 0 r/w 1 p61dr 0 r/w stores output data for port 6 pins (p6 7 to p6 0 ) bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
720 padrport a data register h'ff69 port a 7 pa7dr 0 r/w 6 pa6dr 0 r/w 5 pa5dr 0 r/w 4 pa4dr 0 r/w 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w stores output data for port a pins (pa 7 to pa 0 ) bit initial value read/write : : : pbdrport b data register h'ff6a port b 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w stores output data for port b pins (pb 7 to pb 0 ) bit initial value read/write : : : pcdrport c data register h'ff6b port c 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w stores output data for port c pins (pc 7 to pc 0 ) bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
721 pddrport d data register h'ff6c port d 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 0 pd0dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w stores output data for port d pins (pd 7 to pd 0 ) bit initial value read/write : : : pedrport e data register h'ff6d port e 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w stores output data for port e pins (pe 7 to pe 0 ) bit initial value read/write : : : pfdrport f data register h'ff6e port f 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w stores output data for port f pins (pf 7 to pf 0 ) bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
722 pgdrport g data register h'ff6f port g 7 undefined 6 undefined 5 undefined 4 pg4dr 0 r/w 3 pg3dr 0 r/w 0 pg0dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w stores output data for port g pins (pg 4 to pg 0 ) bit initial value read/write : : : papcrport a mos pull-up control register h'ff70 port a 7 pa7pcr 0 r/w 6 pa6pcr 0 r/w 5 pa5pcr 0 r/w 4 pa4pcr 0 r/w 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w controls the mos input pull-up function incorporated into port a on a bit-by-bit basis bit initial value read/write : : : pbpcrport b mos pull-up control register h'ff71 port b 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w controls the mos input pull-up function incorporated into port b on a bit-by-bit basis bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
723 pcpcrport c mos pull-up control register h'ff72 port c 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w controls the mos input pull-up function incorporated into port c on a bit-b y -bit basis bit initial value read/write : : : pdpcrport d mos pull-up control register h'ff73 port d 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w controls the mos input pull-up function incorporated into port d on a bit-by-bit basis bit initial value read/write : : : pepcrport e mos pull-up control register h'ff74 port e 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w controls the mos input pull-up function incorporated into port e on a bit-by-bit basis bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
724 p3odrport 3 open drain control register h'ff76 port 3 7 undefined 6 undefined 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w controls the pmos on/off status for each port 3 pin (p3 5 to p3 0 ) bit initial value read/write : : : paodrport a open drain control register h'ff77 port a 7 pa7odr 0 r/w 6 pa6odr 0 r/w 5 pa5odr 0 r/w 4 pa4odr 0 r/w 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w controls the pmos on/off status for each port a pin (pa 7 to pa 0 ) bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
725 smr0serial mode register 0 h'ff78 sci0 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 1 asynchronous mode synchronous mode asynchronous mode/synchronous mode select 0 1 parity bit addition and checking disabled parity bit addition and checking enabled parity enable 0 1 even parity odd parity parity mode 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock clock select 0 1 multiprocessor function disabled multiprocessor format selected multiprocessor mode 0 1 1 stop bit 2 stop bits stop bit length 0 1 8-bit data 7-bit data * character length note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
726 smr0serial mode register 0 h'ff78 smart card interface 0 7 gm 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 1 normal smart card interface mode operation tend flag generated 12.5 etu after beginning of start bit clock output on/off control only gsm mode smart card interface mode operation tend flag generated 11.0 etu after beginning of start bit fixed high/low-level control possible (set in scr) in addition to clock output on/off control gsm mode 0 1 setting prohibited parity bit addition and checking enabled parity enable 0 1 even parity odd parity parity mode 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock clock select 0 1 multiprocessor function disabled setting prohibited multiprocessor mode 0 1 setting prohibited 2 stop bits stop bit length 0 1 8-bit data setting prohibited character length bit initial value read/write : : : note: etu (elementary time unit): interval for transfer of one bit www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
727 brr0bit rate register 0 h'ff79 sci0, smart card interface 0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w sets the serial transfer bit rate note: see section 12.2.8, bit rate register (brr), for details. bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
728 scr0serial control register 0 h'ff7a sci0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 0 asynchronous mode internal clock/sck pin functions as i/o port clock enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupt enable 0 1 reception disabled reception enabled receive enable 0 1 transmission disabled transmission enabled transmit enable 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled transmit interrupt enable notes: bit initial value read/write : : : synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input 1. outputs a clock of the same frequency as the bit rate. 2. inputs a clock with a frequency 16 times the bit rate. multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 0 1 1 1 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
729 scr0serial control register 0 h'ff7a smart card interface 0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w smcr smif 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 smr c/ a ,gm cke1 cke0 see sci specification sck pin function clock enable scr setting 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupt enable 0 1 reception disabled reception enabled receive enable 0 1 transmission disabled transmission enabled transmit enable 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled transmit interrupt enable bit initial value read/write : : : multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled operates as port input pin clock output as sck output pin fixed-low output as sck output pin clock output as sck output pin fixed-high output as sck output pin clock output as sck output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
730 tdr0transmit data register 0 h'ff7b sci0, smart card interface 0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w stores data for serial transmission bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
731 ssr0serial status register 0 h'ff7c sci0 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r note: * can onl y be written with 0 for fla g clearin g . 0 transmit data register empty 0 receive data register full 0 overrun error 0 framing error 0 parity error 0 transmit end [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr 0 multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting conditions] ?when the te bit in scr is 0 ?when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 [clearing condition] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting condition] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr 1 1 1 1 1 1 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
732 ssr0serial status register 0 h'ff7c smart card interface 0 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r note: * can onl y be written with 0 for fla g clearin g . 0 transmit data register empty 0 receive data register full 0 overrun error 0 error signal status 0 parity error 0 transmit end [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr 0 multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting conditions] ?on reset, or in standby mode or module stop mode ?when the te bit in scr is 0 and the ers bit is 0 ?when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when gm = 0 ?when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when gm = 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr [clearing condition] ?on reset, or in standby mode or module stop mode ?when 0 is written to ers after reading ers = 1 [setting condition] when the error signal is sampled at the low level [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 [clearing condition] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting condition] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr note: etu: elementary time unit (the time taken to transmit one bit) note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its prior state. 1 1 1 1 1 1 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
733 rdr0receive data register 0 h'ff7d sci0, smart card interface 0 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write : : : stores received serial data scmr0smart card mode register 0 h'ff7e sci0, smart card interface 0 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 0 1 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first smart card data direction 0 1 tdr contents are transmitted as they are receive data is stored in rdr as it is smart card data invert 0 1 smart card interface function is disabled smart card interface mode select bit initial value read/write : : : smart card interface function is enabled tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form tdr contents are transmitted msb-first receive data is stored in rdr msb-first www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
734 smr1serial mode register 1 h'ff80 sci1 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 1 asynchronous mode synchronous mode asynchronous mode/synchronous mode select 0 1 parity bit addition and checking disabled parity bit addition and checking enabled parity enable 0 1 even parity odd parity parity mode 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock clock select 0 1 multiprocessor function disabled multiprocessor format selected multiprocessor mode 0 1 1 stop bit 2 stop bits stop bit length 0 1 8-bit data 7-bit data * character length note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
735 smr1serial mode register 1 h'ff80 smart card interface 1 7 gm 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 1 normal smart card interface mode operation ? tend flag generated 12.5 etu after beginning of start bit ? clock output on/off control only gsm mode smart card interface mode operation ? tend flag generated 11.0 etu after beginning of start bit ? fixed high/low-level control possible (set in scr) in addition to clock output on/off control gsm mode 0 1 setting prohibited parity bit addition and checking enabled parity enable 0 1 even parity odd parity parity mode 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock clock select 0 1 multiprocessor function disabled setting prohibited multiprocessor mode 0 1 setting prohibited 2 stop bits stop bit length 0 1 8-bit data setting prohibited character length bit initial value read/write : : : note: etu (elementary time unit): interval for transfer of one bit www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
736 brr1bit rate register 1 h'ff81 sci1, smart card interface 1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w note: see section 12.2.8, bit rate register (brr), for details. sets the serial transfer bit rate bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
737 scr1serial control register 1 h'ff82 sci1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 1 0 asynchronous mode internal clock/sck pin functions as i/o port clock enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received multiprocessor interrupt enable 0 1 reception disabled reception enabled receive enable 0 1 transmission disabled transmission enabled transmit enable 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled transmit interrupt enable notes: bit initial value read/write : : : synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input 1. outputs a clock of the same frequency as the bit rate. 2. inputs a clock with a frequency 16 times the bit rate. multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled 1 0 1 0 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
738 scr1serial control register 1 h'ff82 smart card interface 1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w smcr smif 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 smr c/ a ,gm cke1 cke0 see sci specification sck pin function clock enable scr setting 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received multiprocessor interrupt enable 0 1 reception disabled reception enabled receive enable 0 1 transmission disabled transmission enabled transmit enable 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled transmit interrupt enable bit initial value read/write : : : multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled operates as port input pin clock output as sck output pin fixed-low output as sck output pin clock output as sck output pin fixed-high output as sck output pin clock output as sck output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
739 tdr1transmit data register 1 h'ff83 sci1, smart card interface 1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w stores data for serial transmission bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
740 ssr1serial status register 1 h'ff84 sci1 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r note: * can only be written with 0 for flag clearing. 0 transmit data register empty 0 receive data register full 0 overrun error 0 framing error 0 parity error 0 transmit end 0 multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting condition] when data with a 1 multiprocessor bit is received [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting condition] ?when the te bit in scr is 0 ?when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr 1 [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 [clearing condition] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting condition] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr 1 1 1 1 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
741 ssr1serial status register 1 h'ff84 smart card interface 1 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r note: * can only be written with 0 for flag clearing. transmit data register empty 0 receive data register full 0 overrun error 0 error signal status 0 parity error 0 transmit end 0 multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting conditions] when data with a 1 multiprocessor bit is received [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?on reset, or in standby mode or module stop mode ?when the te bit in scr is 0 and the ers bit is 0 ?when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when gm = 0 ?when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when gm = 1 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr 1 [clearing condition] ?on reset, or in standby mode or module stop mode ?when 0 is written to ers after reading ers =1 [setting conditions] when the error signal is sampled at the low level [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 [clearing condition] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting condition] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr note: etu: elementary time unit (the time taken to transmit one bit) 1 note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its prior state. 1 1 1 0 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
742 rdr1receive data register 1 h'ff85 sci1, smart card interface 1 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r stores received serial data bit initial value read/write : : : scmr1smart card mode register 1 h'ff86 sci1, smart card interface 1 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 0 1 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first smart card data direction 0 tdr contents are transmitted as they are receive data is stored in rdr as it is smart card data invert 0 1 smart card interface function is disabled smart card interface mode select bit initial value read/write : : : smart card interface function is enabled tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
743 smr2serial mode register 2 h'ff88 sci2 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 1 asynchronous mode synchronous mode asynchronous mode/synchronous mode select 0 1 parity bit addition and checking disabled parity bit addition and checking enabled parity enable 0 1 even parity odd parity parity mode 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock clock select 0 1 multiprocessor function disabled multiprocessor format selected multiprocessor mode 0 1 1 stop bit 2 stop bits stop bit length 0 1 8-bit data 7-bit data * character length note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
744 smr2serial mode register 2 h'ff88 smart card interface 2 7 gm 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 1 normal smart card interface mode operation tend flag generated 12.5 etu after beginning of start bit clock output on/off control only gsm mode smart card interface mode operation tend flag generated 11.0 etu after beginning of start bit fixed high/low-level control possible (set in scr) in addition to clock output on/off control gsm mode 0 1 setting prohibited parity bit addition and checking enabled parity enable 0 1 even parity odd parity parity mode 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock clock select 0 1 multiprocessor function disabled setting prohibited multiprocessor mode 0 1 setting prohibited 2 stop bits stop bit length 0 1 8-bit data setting prohibited character length bit initial value read/write : : : note: etu (elementary time unit): interval for transfer of one bit www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
745 brr2bit rate register 2 h'ff89 sci2, smart card interface 2 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w sets the serial transfer bit rate note: see section 12.2.8, bit rate register (brr), for details. bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
746 scr2serial control register 2 h'ff8a sci2 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w asynchronous mode internal clock/sck pin functions as i/o port clock enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit end interrupt enable multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupt enable 0 1 reception disabled reception enabled receive enable 0 1 transmission disabled transmission enabled transmit enable receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled transmit interrupt enable notes: bit initial value read/write : : : synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input 1. outputs a clock of the same frequency as the bit rate. 2. inputs a clock with a frequency 16 times the bit rate. multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 00 1 0 1 1 0 1 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
747 scr2serial control register 2 h'ff8a smart card interface 2 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w smcr smif 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 smr c/ a ,gm cke1 cke0 see sci specification sck pin function clock enable scr setting 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupt enable 0 1 reception disabled reception enabled receive enable 0 1 transmission disabled transmission enabled transmit enable 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled transmit interrupt enable bit initial value read/write : : : multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled operates as port input pin clock output as sck output pin fixed-low output as sck output pin clock output as sck output pin fixed-high output as sck output pin clock output as sck output pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
748 tdr2transmit data register 2 h'ff8b sci2, smart card interface 2 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w stores data for serial transmission bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
749 ssr2serial status register 2 h'ff8c sci2 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r note: * can only be written with 0 for flag clearing. transmit data register empty receive data register full overrun error framing error parity error transmit end multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting condition] when data with a 1 multiprocessor bit is received [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting condition] ?when the te bit in scr is 0 ?when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 [clearing condition] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting condition] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr 0 1 0 1 0 1 0 1 0 1 0 1 0 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
750 ssr2serial status register 2 h'ff8c smart card interface 2 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r note: * can only be written with 0 for flag clearing. transmit data register empty receive data register full overrun error parity error multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting condition] when data with a 1 multiprocessor bit is received [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] on of the next serial reception when rdrf= 1 completion [clearing condition] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting condition] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr transmit end [clearing condition] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?on reset, or in standby mode or module stop mode ?when the te bit in scr is 0 ?when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when gm = 0 ?when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when gm = 1 note: etu: elementary time unit (the time taken to transmit one bit) 0 error signal status [clearing condition] ?on reset, or in standby mode or module stop mode ?when 0 is written to ers after reading ers =1 [setting conditions] when the error signal is sampled at the low level 1 note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its prior state. 0 1 0 1 0 1 0 1 0 1 0 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
751 rdr2receive data register 2 h'ff8d sci2, smart card interface 2 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r stores received serial data bit initial value read/write : : : scmr2smart card mode register 2 h'ff8e sci2, smart card interface 2 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 0 1 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first smart card data direction 0 1 tdr contents are transmitted as they are receive data is stored in rdr as it is smart card data invert 0 1 smart card interface function is disabled smart card interface mode select bit initial value read/write : : : smart card interface function is enabled tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form tdr contents are transmitted msb-first receive data is stored in rdr msb-first www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
752 addrah a/d data register ah h'ff90 a/d converter addral a/d data register al h'ff91 a/d converter addrbh a/d data register bh h'ff92 a/d converter addrbl a/d data register bl h'ff93 a/d converter addrch a/d data register ch h'ff94 a/d converter addrcl a/d data register cl h'ff95 a/d converter addrdh a/d data register dh h'ff96 a/d converter addrdl a/d data register dl h'ff97 a/d converter 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r stores the results of a/d conversion analog input channel a/d data register bit initial value read/write : : : group 0 an0 an1 an2 an3 group 1 an4 an5 an6 an7 addra addrb addrc addrd www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
753 adcsra/d control/status register h'ff98 a/d converter [clearing conditions] ?when 0 is written to the adf flag after reading adf = 1 ?when the dtc is activated by an adi interrupt, and addr is read 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w note: * can only be written with 0 for flag clearing. 0 1 conversion time= 266 states (max.) conversion time= 134 states (max.) group select 0 1 a/d conversion end interrupt (adi) request disabled a/d conversion end interrupt (adi) request enabled a/d interrupt enable 0 1 single mode scan mode scan mode 0 1 a/d conversion stopped a/d start 0 a/d end flag ch1 0 1 0 1 ch0 0 1 0 1 0 1 0 1 single mode an0 an0, an1 an0 to an2 an0 to an3 an4 an4, an5 an4 to an6 an4 to an7 channel select bit initial value read/write : : : ?single mode: a/d conversion is started. cleared to 0 automatically when conversion ends ?scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or transition to standby mode or module stop mode [setting conditions] ?single mode: when a/d conversion ends ?scan mode: when one round of conversion has been performed on all specified channels 1 ch2 0 1 group select channel select an0 an1 an2 an3 an4 an5 an6 an7 group mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
754 adcra/d control register h'ff99 a/d 7 trgs1 0 r/w 6 trgs0 0 r/w 5 1 4 1 3 1 0 1 2 1 1 1 0 1 0 1 0 description timer trigger select bit initial value read/write : : : a/d conversion start by external trigger is disabled a/d conversion start by external trigger (tpu) is enabled a/d conversion start by external trigger (8-bit timer) is enabled a/d conversion start by external trigger pin ( adtrg ) is enabled 1 trgs1 trgs1 dadr0d/a data register 0 (reserved in h8s/2393) h'ffa4 d/a dadr1d/a data register 1 (reserved in h8s/2393) h'ffa5 d/a 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w stores data for d/a conversion bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
755 dacrd/a control register (reserved in h8s/2393) h'ffa6 d/a 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 d/a conversion control daoe1 daoe0 dae description 0 1 0 1 0 1 * 0 1 0 1 * channel 0 and 1 d/a conversion disabled channel 0 d/a conversion enabled channel 1 d/a conversion disabled channel 0 and 1 d/a conversions enabled channel 0 d/a conversion disabled channel 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled * : don? care 0 1 analog output da0 is disabled channel 0 d/a conversion is enabled d/a output enable 0 0 1 analog output da1 is disabled channel 1 d/a conversion is enabled d/a output enable 1 bit initial value read/write : : : analog output da0 is enabled analog output da1 is enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
756 tcr0time control register 0 h'ffb0 8-bit timer channel 0 tcr1time control register 1 h'ffb1 8-bit timer channel 1 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w note: * 000 1 clock input disabled internal clock: counted at falling edge of ?8 internal clock: counted at falling edge of ?64 10 internal clock: counted at falling edge of ?8192 1 1 0 0 for channel 0: count at tcnt1 overflow signal * for channel 1: count at tcnt0 compare match a * external clock: counted at rising edge external clock: counted at falling edge 1 0 1 external clock: counted at both rising and falling edges 1 clock select 0 1 cmfb interrupt requests (cmib) are disabled cmfb interrupt requests (cmib) are enabled compare match interrupt enable b 0 1 cmfa interrupt requests (cmia) are disabled cmfa interrupt requests (cmia) are enabled compare match interrupt enable a 0 1 ovf interrupt requests (ovi) are disabled ovf interrupt requests (ovi) are enabled timer overflow interrupt enable 0 1 clear is disabled clear by compare match a clear by compare match b clear by rising edge of external reset input 0 1 0 1 counter clear bit initial value read/write if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare match signal, no incrementing clock is generated. do not use this setting. : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
757 tcsr0timer control/status register 0 h'ffb2 8-bit timer channel 0 tcsr1timer control/status register 1 h'ffb3 8-bit timer channel 1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w tcsr1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w tcsr0 note: * only 0 can be written to bits 7 to 5, to clear these flags. 0 1 compare match flag b 0 1 compare match flag a 0 [clearing condition] ?cleared by reading ovf when ovf = 1, then writing 0 to ovf 1 timer overflow flag 0 1 a/d converter start requests by compare match a are disabled a/d converter start requests by compare match a are enabled a/d trigger enable (tcsr0 only) 0 1 no change when compare match b occurs 0 is output when compare match b occurs 1 is output when compare match b occurs 0 1 0 1 output select bit initial value read/write : : : bit initial value read/write : : : [setting condition] set when tcnt overflows (changes from h'ff to h'00) [clearing condition] ?cleared by reading cmfa when cmfa = 1, then writing 0 to cmfa ?when the dtc is activated by a cmia interrupt, while disel bit of mrb in dtc is 0. [setting condition] set when tcnt matches tcora [clearing condition] ?cleared by reading cmfb when cmfb = 1, then writing 0 to cmfb ?when the dtc is activated by a cmib interrupt, while disel bit of mrb in dtc is 0. [setting condition] set when tcnt matches tcorb output is inverted when compare match b occurs (toggle output) 0 no change when compare match a occurs 0 output select output is inverted when compare match a occurs (toggle output) 1 is output when compare match a occurs 0 is output when compare match a occurs 1 1 0 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
758 tcora0time constant register a0 h'ffb4 8-bit timer channel 0 tcora1time constant register a1 h'ffb5 8-bit timer channel 1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 bit initial value read/write : : : tcorb0time constant register b0 h'ffb6 8-bit timer channel 0 tcorb1time constant register b1 h'ffb7 8-bit timer channel 1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 bit initial value read/write : : : tcnt0timer counter 0 h'ffb8 8-bit timer channel 0 tcnt1timer counter 1 h'ffb9 8-bit timer channel 1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 tcnt1 bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
759 tcsrtimer control/status register h'ffbc (w) h'ffbc (r) wdt 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w the method for writing to tcsr is different from that for general registers to prevent accidental overwriting. for details see section 11.2.4, notes on register access. 0 [clearing condition] cleared by reading tcsr when ovf = 1, then writing 0 to ovf 1 overflow flag 0 interval timer mode: sends the cpu an interval timer interrupt request (wovi) when tcnt overflows watchdog timer mode: generates the wdtovf signal when tcnt overflows 1 timer mode select 0 1 tcnt is initialized to h'00 and halted tcnt counts timer enable clock select cks2 cks1 cks0 clock overflow period * (when ?= 20 mhz) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ?2 (initial value) ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 25.6 s 819.2 s 1.6ms 6.6ms 26.2ms 104.9ms 419.4ms 1.68s note: * can only be written with 0 for flag clearing. note: * bit initial value read/write : : : the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. [setting condition] set when tcnt overflows from h'ff to h'00 in interval timer mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
760 tcnttimer counter h'ffbc (w) h'ffbd (r) wdt 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write : : : rstcsrreset control/status register h'ffbe (w) h'ffbf (r) wdt 7 wovf 0 r/(w) * 6 rste 0 r/w 5 rsts 0 r/w 4 1 3 1 0 1 2 1 1 1 0 1 [clearing condition] cleared by reading tcsr when wovf = 1, then writing 0 to wovf watchdog timer overflow flag note: * can only be written with 0 for flag clearing. the method for writing to rstcsr is different from that for general registers to prevent accidental overwriting. for details see section 11.2.4, notes on register access. 0 1 reset enable reset signal is not generated if tcnt overflows * reset signal is generated if tcnt overflows 0 1 reset select power-on reset manual reset bit initial value read/write : : : [setting condition] set when tcnt overflows (changed from h'ff to h'00) during watchdog timer operation note: * the modules h8s/2355 series are not reset, but tcnt and tcsr in wdt are reset. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
761 tstrtimer start register h'ffc0 tpu 7 0 6 0 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w counter start 0 1 tcntn count operation is stopped tcntn performs count operation note: (n = 5 to 0) if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. bit initial value read/write : : : tsyrtimer synchro register h'ffc1 tpu 7 0 6 0 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w timer synchronization 0 1 tcntn operates independently (tcnt presetting/ clearing is unrelated to other channels) (n = 5 to 0) notes: to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. 1. 2. bit initial value read/write : : : tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
762 tcr0timer control register 0 h'ffd0 tpu0 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel counter clear 0 0 1 0 1 0 1 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input external clock: counts on tclkd pin input time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 bit initial value read/write : : : notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 10 1 0 1 0 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
763 tmdr0timer mode register 0 h'ffd1 tpu0 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 1 tgrb buffer operation tgrb operates normally 0 1 tgra buffer operation tgra operates normally 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * notes: 1. 2. md3 is a reserved bit. in a write, it should always be written with 0. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. * : don? care bit initial value read/write : : : tgra and tgrc used together for buffer operation tgrb and tgrd used together for buffer operation www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
764 tior0htimer i/o control register 0h h'ffd2 tpu0 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 1 tgr0b i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 tgr0a is output compare register tgr0a i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges * : don? care * : don? care note: * 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000, and ?1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. bit initial value read/write : : : initial output is 0 output tgr0a is input capture register output disabled initial output is 1 output capture input source is tioca0 pin capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down tgr0b is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr0b is input compare register output disabled initial output is 0 output capture input source is tiocb0 pin capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down * 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
765 tior0ltimer i/o control register 0l h'ffd3 tpu0 0 1 tgr0d i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 tgr0c i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * * : don? care * : don? care notes: when bits tpsc2 to tpsc0 in tcr1 are set to b'000, and ?1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 1 2 note: when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer regis ter. bit initial value read/write : : : : tgr0c is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr0c is input capture register output disabled initial output is 1 output capture input source is tiocc0 pin capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down tgr0d is output compare register * 2 output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr0d is input capture register * 2 output disabled initial output is 1 output capture input source is tiocd0 pin capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down * 1 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
766 tier0timer interrupt enable register 0 h'ffd4 tpu0 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled overflow interrupt enable tgr interrupt enable d tgr interrupt enable c tgr interrupt enable b 0 1 interrupt requests (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled 0 1 interrupt requests (tgic) by tgfc bit disabled 0 1 interrupt requests (tgid) by tgfd bit disabled bit initial value read/write : : : interrupt requests (tgia) by tgfa bit enabled interrupt requests (tgib) by tgfb bit enabled interrupt requests (tgic) by tgfc bit enabled interrupt requests (tgid) by tgfd bit enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
767 tsr0timer status register 0 h'ffd5 tpu0 7 1 6 1 5 0 4 tcfv 0 r/(w)* 3 tgfd 0 r/(w)* 0 tgfa 0 r/(w)* 2 tgfc 0 r/(w)* 1 tgfb 0 r/(w)* note: * can only be written with 0 for flag clearing. 0 overflow flag 1 0 input capture/output compare flag d 1 0 input capture/output compare flag c 1 0 input capture/output compare flag b 1 0 [clearing condition] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 bit initial value read/write : : : [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing condition] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing condition] ?when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfc after reading tgfc = 1 [setting conditions] ?when tcnt = tgrc while tgrc is functioning as output compare register ?when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register [clearing condition] ?when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfd after reading tgfd = 1 [setting conditions] ?when tcnt = tgrd while tgrd is functioning as output compare register ?when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting conditions] when the tcnt value overflows (changes from h'ffff to h'0000 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
768 tcnt0timer counter 0 h'ffd6 tpu0 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up-counter tgr0atimer general register 0a h'ffd8 tpu0 tgr0btimer general register 0b h'ffda tpu0 tgr0ctimer general register 0c h'ffdc tpu0 tgr0dtimer general register 0d h'ffde tpu0 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
769 tcr1timer control register 1 h'ffe0 tpu1 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 0 1 0 1 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkb pin input internal clock: counts on ?256 counts on tcnt2 overflow/underflow time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: this setting is ignored when channel 1 is in phase counting mode. note: * synchronous operating setting is performed by setting the sync bit in tsyr to 1. bit initial value read/write : : : note: this setting is ignored when channel 1 is in phase counting mode. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
770 tmdr1timer mode register 1 h'ffe1 tpu1 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 1phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * notes: md3 is a reserved bit. in a write, it should always be written with 0. * : don? care 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
771 tior1timer i/o control register 1 h'ffe2 tpu1 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 1 tgr1b i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * tgr1a i/o control * : don? care 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * * : don? care bit initial value read/write : : : tgr1a is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr1a is input capture register output disabled initial output is 1 output capture input source is tioca1 pin capture input source is tgr0a compare match/ input capture input capture at generation of channel 0/tgr0a compare match/ input capture tgr1b is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr1b is input capture register output disabled initial output is 1 output capture input source is tiocb1 pin capture input source is tgr0c compare match/ input capture input capture at generation of tgr0b compare match/input capture www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
772 tier1timer interrupt enable register 1 h'ffe4 tpu1 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled underflow interrupt enable tgr interrupt enable b 0 1 interrupt requests (tgia) by tgfa bit disabled tgi interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled overflow interrupt enable bit initial value read/write : : : interrupt requests (tgia) by tgfa bit enabled interrupt requests (tgib) by tgfb bit enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
773 tsr1timer status register 1 h'ffe5 tpu1 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w)* 2 0 1 tgfb 0 r/(w)* 0 1 tcnt counts down tcnt counts up count direction flag 0 underflow flag 1 0 overflow flag 1 0 input capture/output compare flag b 1 0 [clearing condition] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 note: * can only be written with 0 for flag clearing. bit initial value read/write : : : [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing condition] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting conditions] when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting conditions] when the tcnt value underflows (changes from h'0000 to h'ffff) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
774 tcnt1timer counter 1 h'ffe6 tpu1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * up/down-counter * bit initial value read/write : : : this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. tgr1atimer general register 1a h'ffe8 tpu1 tgr1btimer general register 1b h'ffea tpu1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
775 tcr2timer control register 2 h'fff0 tpu2 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 0 1 0 1 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input internal clock: counts on ?1024 time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: this setting is ignored when channel 2 is in phase counting mode. note: * synchronous operating setting is performed by setting the sync bit tsyr to 1. bit initial value read/write : : : note: this setting is ignored when channel 2 is in phase counting mode. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
776 tmdr2timer mode register 2 h'fff1 tpu2 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * notes: md3 is a reserved bit. in a write, it should always be written with 0. * : don? care 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
777 tior2timer i/o control register 2 h'fff2 tpu2 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 1 tgr2b i/o control 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * : don? care 0 1 tgr2a is output compare register tgr2a i/o control 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges * : don? care bit initial value read/write : : : output disabled initial output is 0 output output disabled initial output is 1 output tgr2a is input capture register capture input source is tioca2 pin tgr2b is output compare register 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges output disabled initial output is 0 output output disabled initial output is 1 output tgr2b is input capture register capture input source is tiocb2 pin www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
778 tier2timer interrupt enable register 2 h'fff4 tpu2 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled underflow interrupt enable tgr interrupt enable b 0 1 interrupt requests (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled overflow interrupt enable bit initial value read/write : : : interrupt requests (tgia) by tgfa bit enabled interrupt requests (tgib) by tgfb bit enabled www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
779 tsr2timer status register 2 h'fff5 tpu2 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * 0 1 tcnt counts down tcnt counts up count direction flag 0 underflow flag 1 0 overflow flag 1 0 input capture/output compare flag b 1 0 [clearing condition] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 note: * can only be written with 0 for flag clearing. bit initial value read/write : : : [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing condition] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting conditions] when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting conditions] when the tcnt value underflows (changes from h'0000 to h'ffff) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
780 tcnt2timer counter 2 h'fff6 tpu2 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. up/down-counter * bit initial value read/write : : : tgr2atimer general register 2a h'fff8 tpu2 tgr2btimer general register 2b h'fffa tpu2 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write : : : www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
781 appendix c i/o port block diagrams c.1 port 1 block diagram r p1nddr c qd reset wddr1 reset wdr1 r p1ndr c qd p1 n rdr1 rpor1 internal data bus tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input wddr1 wdr1 rdr1 rpor1 n = 0, 1, 4, and 6 legend : write to p1ddr : write to p1dr : read p1dr : read port 1 figure c-1 (a) port 1 block diagram (pins p1 0 , p1 1 , p1 4 and p1 6 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
782 r p1nddr c qd reset wddr1 reset wdr1 r p1ndr c qd p1 n rdr1 rpor1 internal data bus tpu module output compare output/ pwm output enable output compare output/ pwm output external clock input input capture input wddr1 wdr1 rdr1 rpor1 n = 2, 3, 5, 7 : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-1 (b) port 1 block diagram (pins p1 2 , p1 3 , p1 5 , and p1 7 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
783 c.2 port 2 block diagram r p2nddr c qd reset wddr2 reset wdr2 r p2ndr c qd p2 n rdr2 rpor2 internal data bus tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input wddr2 wdr2 rdr2 rpor2 n = 0 or 1 : write to p2ddr : write to p2dr : read p2dr : read port 2 legend figure c-2 (a) port 2 block diagram (pins p2 0 and p2 1 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
784 r p2nddr c qd reset wddr2 reset wdr2 r p2ndr c qd p2 n rdr2 rpor2 internal data bus tpu module output compare output/ pwm output enable counter external reset input output compare output/ pwm output 8-bit timer module input capture input wddr2 wdr2 rdr2 rpor2 n = 2 or 4 : write to p2ddr : write to p2dr : read p2dr : read port 2 legend figure c-2 (b) port 2 block diagram (pins p2 2 and p2 4 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
785 r p2nddr c qd reset wddr2 reset wdr2 r p2ndr c qd p2 n rdr2 rpor2 internal data bus tpu module output compare output/ pwm output enable counter external clock input output compare output/ pwm output 8-bit timer module input capture input wddr2 wdr2 rdr2 rpor2 n = 3 or 5 : write to p2ddr : write to p2dr : read p2dr : read port 2 legend figure c-2 (c) port 2 block diagram (pins p2 3 and p2 5 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
786 r p2nddr c qd reset wddr2 reset wdr2 r p2ndr c qd p2 n rdr2 rpor2 internal data bus 8-bit timer tpu module compare-match output enable compare-match output output compare output/ pwm output enable output compare output/ pwm output input capture input wddr2 wdr2 rdr2 rpor2 n = 6 or 7 : write to p2ddr : write to p2dr : read p2dr : read port 2 legend figure c-2 (d) port 2 block diagram (pins p2 6 and p2 7 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
787 c.3 port 3 block diagram r p3nddr c qd reset wddr3 reset wdr3 r c qd p3 n rdr3 rodr3 rpor3 internal data bus sci module serial transmit enable serial transmit data wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 0 or 1 notes: 1. output enable signal 2. open drain control signal : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr p3ndr reset wodr3 r c qd p3nodr * 1 * 2 legend figure c-3 (a) port 3 block diagram (pins p3 0 and p3 1 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
788 r p3nddr c qd reset wddr3 reset wdr3 r c qd p3 n rdr3 rodr3 rpor3 internal data bus sci module serial receive data enable serial receive data wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 2 or 3 notes: 1. output enable signal 2. open drain control signal : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr p3ndr reset wodr3 r c qd p3nodr * 1 * 2 legend figure c-3 (b) port 3 block diagram (pins p3 2 and p3 3 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
789 r p3nddr c qd reset wddr3 reset wdr3 r c qd p3 n rdr3 rodr3 rpor3 internal data bus sci module serial clock output enable serial clock output serial clock input enable serial clock input wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 4 or 5 notes: 1. priority order: serial clock input > serial clock output > dr output 2. output enable signal 3. open drain control signal : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr p3ndr reset wodr3 r c qd p3nodr * 2 * 3 * 1 legend figure c-3 (c) port 3 block diagram (pins p3 4 and p3 5 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
790 c.4 port 4 block diagram p4 n rpor4 internal data bus a/d converter module analog input rpor4 n = 0 to 5 : read port 4 figure c-4 (a) port 4 block diagram (pins p4 0 to p4 5 in h8s/2355 and h8s/2353, pins p4 0 to p4 7 in h8s/2393) p4 n rpor4 internal data bus a/d converter module analog input d/a converter module output enable analog output rpor4 n = 6 or 7 : read port 4 figure c-4 (b) port 4 block diagram (pins p4 6 and p4 7 in h8s/2355 and h8s/2353) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
791 c.5 port 5 block diagram r p50ddr c qd reset wddr0 reset wdr5 r c qd p5 0 rdr5 rpor5 internal data bus sci module serial transmit data output enable serial transmit data wddr5 wdr5 rdr5 rpor5 : write to p5ddr : write to p5dr : read p5dr : read port 5 p50dr legend figure c-5 (a) port 5 block diagram (pin p5 0 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
792 r p51ddr c qd reset wddr5 reset wdr5 r c qd p5 1 rdr5 rpor5 internal data bus sci module serial receive data enable serial receive data wddr5 wdr5 rdr5 rpor5 : write to p5ddr : write to p5dr : read p5dr : read port 5 p51dr legend figure c-5 (b) port 5 block diagram (pin p5 1 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
793 r p52ddr c qd reset wddr5 reset wdr5 r c qd p5 2 internal data bus sci module serial clock output enable serial clock output serial clock input enable serial clock input wddr5 wdr5 rdr5 rpor5 : write to p5ddr : write to p5dr : read p5dr : read port 5 p52dr rdr5 rpor5 legend figure c-5 (c) port 5 block diagram (pin p5 2 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
794 r p53ddr c qd reset wddr5 reset wdr5 r c qd p5 3 rdr5 rpor5 internal data bus a/d converter a/d converter external trigger input wddr5 wdr5 rdr5 rpor5 legend : write to p5ddr : write to p5dr : read p5dr : read port 5 p53dr figure c-5 (d) port 5 block diagram (pin p5 3 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
795 c.6 port 6 block diagram r p6nddr c qd reset wddr6 mode 1/2/3/7 mode 4/5/6 reset wdr6 r p6ndr c qd p6 n rdr6 rpor6 internal data bus bus controller chip select wddr6 wdr6 rdr6 rpor6 n = 0 or 1 : write to p6ddr : write to p6dr : read p6dr : read port 6 legend figure c-6 (a) port 6 block diagram (pins p6 0 and p6 1 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
796 r p6nddr c qd reset wddr6 reset wdr6 r p6ndr c qd p6 n rdr6 rpor6 internal data bus wddr6 wdr6 rdr6 rpor6 n = 2 or 3 : write to p6ddr : write to p6dr : read p6dr : read port 6 legend figure c-6 (b) port 6 block diagram (pins p6 2 and p6 3 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
797 r p6nddr c qd reset wddr6 reset wdr6 r p6ndr c qd p6 n rdr6 rpor6 internal data bus interrupt controller irq interrupt input wddr6 wdr6 rdr6 rpor6 n = 4 or 5 : write to p6ddr : write to p6dr : read p6dr : read port 6 legend figure c-6 (c) port 6 block diagram (pins p6 4 and p6 5 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
798 r p6nddr c qd reset wddr6 mode 1/2/3/7 mode 4/5/6 reset wdr6 r p6ndr c qd p6 n rdr6 rpor6 internal data bus interrupt controller bus controller chip select irq interrupt input wddr6 wdr6 rdr6 rpor6 n = 6 or 7 : write to p6ddr : write to p6dr : read p6dr : read port 6 legend figure c-6 (d) port 6 block diagram (pins p6 6 and p6 7 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
799 c.7 port a block diagram r panpcr c qd reset wpcra reset wdra r c qd pa n rdra rodra rpora internal data bus internal address bus wddra wdra wodra wpcra rdra rpora rodra rpcra n = 0 to 3 : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr pandr reset wddra r mode 4/5 * 3 s c qd panddr reset wodra rpcra r c qd panodr * 1 * 2 mode 1/2/3/6/7 mode 4/5 notes: 1. output enable signal 2. open drain control signal 3. set priority legend figure c-7 (a) port a block diagram (pins pa 0 to pa 3 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
800 r pa4pcr c qd reset wpcra reset wdra r c qd pa 4 rdra rodra rpora internal data bus internal address bus wddra wdra wodra wpcra rdra rpora rodra rpcra : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr pa4dr reset wddra r mode 4/5 * 3 s c qd pa4ddr reset wodra rpcra r c qd pa4odr * 1 * 2 mode 1/2/3/6/7 mode 4/5 interrupt controller irq interrupt input notes: 1. output enable signal 2. open drain control signal 3. set priority legend figure c-7 (b) port a block diagram (pin pa 4 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
801 r panpcr c qd reset wpcra reset wdra r c qd pa n rdra rodra rpora internal data bus internal address bus wddra wdra wodra wpcra rdra rpora rodra rpcra n = 5 to 7 : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr pandr wddra c qd panddr reset wodra rpcra r c qd panodr * 1 * 2 mode 1/2/3/6/7 mode 4/5 interrupt controller irq interrupt input reset r notes: 1. output enable signal 2. open drain control signal legend figure c-7 (c) port a block diagram (pins pa 5 to pa 7 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
802 c.8 port b block diagram r pbnpcr c qd reset wpcrb reset wdrb r c qd pb n rdrb rporb internal data bus internal address bus wddrb wdrb wpcrb rdrb rporb rpcrb n = 0 to 7 note: * set priority : write to pbddr : write to pbdr : write to pbpcr : read pbdr : read port b : read pbpcr pbndr reset wddrb r mode 1/4/5 * s c qd pbnddr rpcrb mode 3/7 mode 1/2/4/5/6 legend figure c-8 port b block diagram (pin pb n ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
803 c.9 port c block diagram r pcnpcr c qd reset wpcrc reset wdrc r c qd pc n rdrc rporc pcndr reset wddrc r mode 1/4/5 * s c qd pcnddr rpcrc mode 3/7 mode 1/2/4/5/6 internal data bus internal address bus wddrc wdrc wpcrc rdrc rporc rpcrc n = 0 to 7 note: * set priorit y : write to pcddr : write to pcdr : write to pcpcr : read pcdr : read port c : read pcpcr legend figure c-9 port c block diagram (pin pc n ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
804 c.10 port d block diagram r pdnpcr c qd reset wpcrd reset wdrd r c qd pd n rdrd rpord internal upper data bus internal lower data bus external address upper write wddrd wdrd wpcrd rdrd rpord rpcrd n = 0 to 7 : write to pdddr : write to pddr : write to pdpcr : read pddr : read port d : read pdpcr pdndr wddrd c qd pdnddr rpcrd mode 3/7 mode 1/2/4/5/6 external address write reset r external address upper read external address lower read external address lower write legend figure c-10 port d block diagram (pin pd n ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
805 c.11 port e block diagram r penpcr c qd reset wpcre reset wdre r c qd pe n rdre rpore pendr wddre c qd penddr rpcre reset r internal upper data bus internal lower data bus mode 3/7 mode 1/2/4/5/6 external address write external address lower read wddre wdre wpcre rdre rpore rpcre n = 0 to 7 : write to peddr : write to pedr : write to pepcr : read pedr : read port e : read pepcr legend figure c-11 port e block diagram (pin pe n ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
806 c.12 port f block diagram r pf0ddr c qd reset wddrf reset wdrf r c qd pf 0 rdrf rporf internal data bus bus request input wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f pf0dr bus controller brle bit mode 1/2/4/5/6 legend figure c-12 (a) port f block diagram (pin pf 0 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
807 r pf1ddr c qd reset wddrf mode 1/2/4/5/6 reset wdrf r pf1dr c qd pf 1 rdrf rporf internal data bus bus controller brle output bus request acknowledge output wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f legend figure c-12 (b) port f block diagram (pin pf 1 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
808 r pf2ddr c qd reset wddrf reset wdrf r pf2dr c qd pf 2 rdrf rporf internal data bus wait input wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f bus controller wait enable mode 1/2/4/5/6 legend figure c-12 (c) port f block diagram (pin pf 2 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
809 r pf3ddr c qd reset wddrf mode 1/2/4/5/6 reset wdrf r pf3dr c qd pf 3 rdrf rporf internal data bus bus controller lwr output wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f mode 3/7 mode 1/2/4/5/6 legend figure c-12 (d) port f block diagram (pin pf 3 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
810 r pf4ddr c qd reset wddrf mode 1/2/4/5/6 reset wdrf r pf4dr c qd pf 4 rdrf rporf internal data bus bus controller hwr output wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f mode 3/7 mode 1/2/4/5/6 legend figure c-12 (e) port f block diagram (pin pf 4 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
811 r pf5ddr c qd reset wddrf mode 1/2/4/5/6 reset wdrf r pf5dr c qd pf 5 rdrf rporf internal data bus bus controller rd output wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f mode 3/7 mode 1/2/4/5/6 legend figure c-12 (f) port f block diagram (pin pf 5 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
812 r pf6ddr c qd reset wddrf mode 1/2/4/5/6 reset wdrf r pf6dr c qd pf 6 rdrf rporf internal data bus bus controller as output wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f mode 3/7 mode 1/2/4/5/6 legend figure c-12 (g) port f block diagram (pin pf 6 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
813 wddrf reset wdrf r pf7dr c qd pf 7 rdrf rporf internal data bus wddrf wdrf rdrf rporf note: * set priority reset r mode 1/2/4/5/6 * s c q pf7ddr : write to pfddr : write to pfdr : read pfdr : read port f d legend figure c-12 (h) port f block diagram (pin pf 7 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
814 c.13 port g block diagram r pg0ddr c qd reset wddrg reset wdrg r pg0dr c qd pg 0 rdrg rporg internal data bus wddrg wdrg rdrg rporg : write to pgddr : write to pgdr : read pgdr : read port g legend figure c-13 (a) port g block diagram (pin pg 0 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
815 r pgnddr c qd reset wddrg reset wdrg r pgndr c qd pg n rdrg rporg internal data bus bus controller chip select wddrg wdrg rdrg rporg n = 1, 2, 3 : write to pgddr : write to pgdr : read pgdr : read port g mode 1/2/3/7 mode 4/5/6 legend figure c-13 (b) port g block diagram (pins pg 1 to pg 3 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
816 wddrg reset wdrg r pg4dr c qd pg 4 rdrg rporg internal data bus bus controller chip select wddrg wdrg rdrg rporg : write to pgddr : write to pgdr : read pgdr : read port g mode 3/7 mode 1/2/4/5/6 reset r mode 1/4/5 mode 2/3/6/7 s c pg4ddr qd legend figure c-13 (c) port g block diagram (pin pg 4 ) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
817 appendix d pin states d.1 port states in each mode table d-1 i/o port states in each processing state port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode bus release state program execution state sleep mode port 1 1 to 7 t kept t kept kept i/o port port 2 1 to 7 t kept t kept kept i/o port port 3 1 to 7 t kept t kept kept i/o port p4 7 /da1 1 to 7 t t t [daoe1 = 1] kept [daoe1 = 0] t kept i/o port p4 6 /da0 1 to 7 t t t [daoe0 = 1] kept [daoe0 = 0] t kept i/o port p4 5 to p4 0 1 to 7 t t t t t input port port 5 1 to 7 t kept t kept kept i/o port p6 5 to p6 2 1 to 7 t kept t kept kept i/o port p6 7 / cs7 1 to 3, 7 t kept t kept kept i/o port p6 6 / cs6 p6 1 / cs5 p6 0 / cs4 4 to 6 t kept t [ddr ope = 0] t [ddr ope = 1] h t [ddr = 0] input port [ddr = 1] cs 7 to cs 4 port a 1 to 3, 7 t kept t kept kept i/o port 4, 5 l kept t [ope = 0] t [ope = 1] kept t address output 6 t kept t [ddr ope = 0] t [ddr ope = 1] kept t [ddr = 0] input port [ddr = 1] address output www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
818 port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode bus release state program execution state sleep mode port b 1, 4, 5 l kept t [ope = 0] t [ope = 1] kept t address output 2, 6 t kept t [ddr ope = 0] t [ddr ope = 1] kept t [ddr = 0] input port [ddr = 1] address output 3, 7 t kept t kept kept i/o port port c 1, 4, 5 l kept t [ope = 0] t [ope = 1] kept t address output 2, 6 t kept t [ddr ope = 0] t [ddr ope = 1] kept t [ddr = 0] input port [ddr = 1] address output 3, 7 t kept t kept kept i/o port port d 1, 2, 4 to 6 t t * t t t data bus 3, 7 t kept t kept kept i/o port port e 1, 2, 4 to 6 8 bit bus t kept t kept kept i/o port 16 bit bus tt * t t t data bus 3, 7 t kept t kept kept i/o port pf 7 /? 1, 2, 4 to 6 clock output [ddr = 0] t [ddr = 1] clock output t [ddr = 0] input port [ddr = 1] h [ddr = 0] input port [ddr = 1] clock output [ddr = 0] input port [ddr = 1] clock output 3, 7 t kept t [ddr = 0] input port [ddr = 1] h [ddr = 0] input port [ddr = 1] clock output [ddr = 0] input port [ddr = 1] clock output www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
819 port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode bus release state program execution state sleep mode pf 6 / as pf 5 / rd pf 4 / hwr pf 3 / lwr 1, 2, 4 to 6 h h * t [ope = 0] t [ope = 1] h t as , rd , hwr , lwr 3, 7 t kept t kept kept i/o port pf 2 / wait 1, 2, 4 to 6 t [waite = 0] kept [waite = 1] t t [waite = 0] kept [waite = 1] t [waite = 0] kept [waite = 1] t [waite = 0] i/o port [waite = 1] wait 3, 7 t kept t kept kept i/o port pf 1 / back 1, 2, 4 to 6 t [brle = 0] kept [brle = 1] back t [brle = 0] kept [brle = 1] h l [brle = 0] i/o port [brle = 1] back 3, 7 t kept t kept kept i/o port pf 0 / breq 1, 2, 4 to 6 t [brle = 0] kept [brle = 1] breq t [brle = 0] kept [brle = 1] t t [brle = 0] i/o port [brle = 1] breq 3, 7 t kept t kept kept i/o port pg 4 / cs0 1, 4, 5 h [ddr = 0] t [ddr ope = 0] t [ddr = 0] 2, 6 t t [ddr = 1] h * t [ddr ope = 1] h input port [ddr = 1] cs 0 3, 7 t kept t kept kept i/o port pg 3 / cs1 1 to 3, 7 t kept t kept kept i/o port pg 2 / cs2 pg 1 / cs3 4 to 6 t [ddr = 0] t [ddr = 1] h * t [ddr ope = 0] t [ddr ope = 1] h t [ddr = 0] input port [ddr = 1] cs 1 to cs 3 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
820 port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode bus release state program execution state sleep mode pg 0 1 to 3, 7 t kept t kept kept i/o port 4 to 6 t kept t kept t i/o port legend: h : high level l : low level t : high impedance kept : input port becomes high-impedance, output port retains state ddr : data direction register ope : output port enable waite : wait input enable brle : bus release enable drame : dram space setting note: * indicates the state after completion of the executing bus cycle. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
821 appendix e pin states at power-on note that pin states at power-on depend on the state of the stby pin and nmi pin. the case in which pins settle* from an indeterminate state at power-on, and the case in which pins settle* from the high-impedance state, are described below. after reset release, power-on reset exception handling is started. note: * settle refers to the pin states in a power-on reset in each mcu operating mode. e.1 when pins settle from an indeterminate state at power-on when the nmi pin level changes from low to high after powering on, the chip goes to the power- on reset state after a high level is detected at the nmi pin. while the chip detects a low level at the nmi pin, the manual reset state is established. the pin states are indeterminate during this interval. (ports may output an internally determined value after powering on.) the nmi setup time (t nmis ) is necessary for the chip to detect a high level at the nmi pin. v cc stby nmi res f power-on reset t osc1 nmi = low ? nmi = high res = low manual reset figure e-1 when pins settle from an indeterminate state at power-on www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
822 e.2 when pins settle from the high-impedance state at power-on when the stby pin level changes from low to high after powering on, the chip goes to the power- on reset state after a high level is detected at the stby pin. while the chip detects a low level at the stby pin, it is in the hardware standby mode. during this interval, the pins are in the high- impedance state. after detecting a high level at the stby pin, the chip starts oscillation. v cc nmi f power-on reset t osc1 nmi = high res = low t1 confirm t1min and t nmis . hardware standby mode stby res figure e-2 when pins settle from the high-impedance state at power-on www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
823 appendix f timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low at least 10 states before the stby signal goes low, as shown below. res must remain low until stby signal goes low (delay from stby low to res high: 0 ns or more). stby res t 2 3 0ns t 1 3 10t cyc figure f-1 timing of transition to hardware standby mode (2) to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained, res does not have to be driven low as in (1). timing of recovery from hardware standby mode drive the res signal low and the nmi signal high approximately 100 ns or more before stby goes high to execute a power-on reset. stby res t osc t nmirh t 3 100ns nmi figure f-2 timing of recovery from hardware standby mode www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
824 appendix g product code lineup table g.1 h8s/2355 series product code lineup product type product code mark code package (hitachi package code) h8s/2355 mask rom hd6432355 hd6432355( *** )te 120-pin tfp (tfp-120) hd6432355( *** )f 128-pin fp (fp-128) ztat tm hd6472355 hd6472355te 120-pin tfp (tfp-120) hd6472355f 128-pin fp (fp-128) h8s/2353 mask rom hd6432353 hd6432353( *** )te 120-pin tfp (tfp-120) hd6432353( *** )f 128-pin fp (fp-128) h8s/2393 mask rom hd6432393 hd6432393( *** )te 120-pin tfp (tfp-120) hd6432393( *** )f 120-pin fp (fp-128) note: ( *** ) is the rom code. see table 1.1, product lineup, for details. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
825 appendix h package dimensions figures h-1 and h-2 show the tfp-120 and fp-128 package dimensions of the h8s/2355 series. hitachi code jedec eiaj weight (reference value) tfp-120 conforms 0.5 g unit: mm *dimension including the plating thickness base material dimension 16.0 0.2 14 0.07 0.10 0.5 0.1 16.0 0.2 0.4 0.10 0.10 1.20 max *0.17 0.05 0 ?8 90 61 130 91 120 31 60 m *0.17 0.05 1.0 1.00 1.2 0.15 0.04 0.15 0.04 figure h-1 tfp-120 package dimensions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
826 hitachi code jedec eiaj weight (reference value) fp-128 1.7 g unit: mm *dimension including the plating thickness base material dimension 0.10 m 20 16.0 0.2 65 38 128 0.5 0.10 1.0 0.5 0.2 3.15 max 0 ?10 22.0 0.2 102 64 39 103 1 *0.22 0.05 14 *0.17 0.05 2.70 0.10 +0.15 ?.10 0.75 0.75 0.20 0.04 0.15 0.04 figure h-2 fp-128 package dimensions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
h8s/2355 series hardware manual publication date: 1st edition, april 1997 3rd edition, february 2000 published by: electronic devices sales & marketing group semiconductor & integrated circuits edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com

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